| Line 1... |
Line 1... |
// Potrebno narediti STALL procesorja pri read-u in write-u
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// Potrebno racunati crc kadar je izbran trace. Ko delamo read iz bufferja
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// Potrebno racunati crc kadar je izbran trace. Ko delamo read iz bufferja
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// Dodati registre RISCOP
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_top.v ////
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//// dbg_top.v ////
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| Line 49... |
Line 47... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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// Headers changed. All additional information is now avaliable in the README.txt file.
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| Line 65... |
Line 66... |
`include "dbg_timescale.v"
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`include "dbg_timescale.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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// Top module
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// Top module
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module dbg_top(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO, P_PowerONReset, Mclk, RISC_ADDR, RISC_DATA_IN,
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module dbg_top(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO, P_PowerONReset, Mclk, RISC_ADDR, RISC_DATA_IN,
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RISC_DATA_OUT, RISC_CS, RISC_RW, Wp, Bp, OpSelect, LsStatus, IStatus
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RISC_DATA_OUT, RISC_CS, RISC_RW, Wp, Bp, OpSelect, LsStatus, IStatus,
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RISC_STALL_O, RISC_RESET_O, BS_CHAIN_I
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input P_TMS, P_TCK;
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input P_TMS, P_TCK;
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| Line 79... |
Line 81... |
input [31:0] RISC_DATA_IN;
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input [31:0] RISC_DATA_IN;
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input [10:0] Wp;
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input [10:0] Wp;
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input Bp;
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input Bp;
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input [3:0] LsStatus;
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input [3:0] LsStatus;
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input [1:0] IStatus;
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input [1:0] IStatus;
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input BS_CHAIN_I;
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output P_TDO;
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output P_TDO;
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output [31:0] RISC_ADDR;
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output [31:0] RISC_ADDR;
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output [31:0] RISC_DATA_OUT;
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output [31:0] RISC_DATA_OUT;
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output [`OPSELECTWIDTH-1:0] OpSelect;
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output [`OPSELECTWIDTH-1:0] OpSelect;
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output RISC_CS; // CS for accessing RISC registers
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output RISC_CS; // CS for accessing RISC registers
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output RISC_RW; // RW for accessing RISC registers
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output RISC_RW; // RW for accessing RISC registers
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output RISC_STALL_O; // Stalls the RISC
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output RISC_RESET_O; // Resets the RISC
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reg [31:0] RISC_ADDR;
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reg [31:0] RISC_ADDR;
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reg [31:0] ADDR;
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reg [31:0] ADDR;
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reg [31:0] RISC_DATA_OUT;
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reg [31:0] RISC_DATA_OUT;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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| Line 155... |
Line 160... |
reg DisableReadBuffer_Mclk; // Incrementing trace read buffer can be active for one MClk clock. Then it is disabled.
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reg DisableReadBuffer_Mclk; // Incrementing trace read buffer can be active for one MClk clock. Then it is disabled.
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// Outputs from registers
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// Outputs from registers
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wire ContinMode;
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wire ContinMode;
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wire TraceEnable;
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wire TraceEnable;
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wire RecSelDepend;
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|
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wire [10:0] WpTrigger;
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wire [10:0] WpTrigger;
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wire BpTrigger;
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wire BpTrigger;
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wire [3:0] LSSTrigger;
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wire [3:0] LSSTrigger;
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wire [1:0] ITrigger;
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wire [1:0] ITrigger;
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| Line 190... |
Line 194... |
wire WpStopValid;
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wire WpStopValid;
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wire BpStopValid;
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wire BpStopValid;
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wire LSSStopValid;
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wire LSSStopValid;
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wire IStopValid;
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wire IStopValid;
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|
|
wire [10:0] RecordPC_Wp;
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wire RecordPC;
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wire [10:0] RecordLSEA_Wp;
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wire RecordLSEA;
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wire [10:0] RecordLDATA_Wp;
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wire RecordLDATA;
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wire [10:0] RecordSDATA_Wp;
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wire RecordSDATA;
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wire [10:0] RecordReadSPR_Wp;
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wire RecordReadSPR;
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wire [10:0] RecordWriteSPR_Wp;
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wire RecordWriteSPR;
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wire [10:0] RecordINSTR_Wp;
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wire RecordINSTR;
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|
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wire RecordPC_Bp;
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wire RecordLSEA_Bp;
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wire RecordLDATA_Bp;
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wire RecordSDATA_Bp;
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wire RecordReadSPR_Bp;
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wire RecordWriteSPR_Bp;
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wire RecordINSTR_Bp;
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// End: Outputs from registers
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// End: Outputs from registers
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|
|
wire TraceTestScanChain; // Trace Test Scan chain selected
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wire TraceTestScanChain; // Trace Test Scan chain selected
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|
|
wire [47:0] Trace_Data;
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wire [47:0] Trace_Data;
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|
|
`endif
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`endif
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wire RiscStall_reg;
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wire RiscReset_reg;
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wire RiscStall_trace;
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|
|
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wire RegisterScanChain; // Register Scan chain selected
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wire RegisterScanChain; // Register Scan chain selected
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wire RiscDebugScanChain; // Risc Debug Scan chain selected
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wire RiscDebugScanChain; // Risc Debug Scan chain selected
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|
| Line 725... |
Line 724... |
|
|
assign RISC_CS = RISCAccess & ~RISCAccess_q;
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assign RISC_CS = RISCAccess & ~RISCAccess_q;
|
assign RISC_RW = RW;
|
assign RISC_RW = RW;
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`ifdef TRACE_ENABLED
|
|
assign RISC_STALL_O = RISC_CS | RiscStall_reg | RiscStall_trace ;
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`else
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assign RISC_STALL_O = RISC_CS | RiscStall_reg;
|
|
`endif
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|
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assign RISC_RESET_O = RiscReset_reg;
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reg [31:0] RISC_DATA_IN_TEMP;
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reg [31:0] RISC_DATA_IN_TEMP;
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// Latching data read from RISC
|
// Latching data read from RISC
|
always @ (posedge Mclk or posedge RESET)
|
always @ (posedge Mclk or posedge RESET)
|
begin
|
begin
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if(RESET)
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if(RESET)
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| Line 805... |
Line 813... |
* End: Bypass logic *
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* End: Bypass logic *
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* *
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* *
|
**********************************************************************************/
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**********************************************************************************/
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/**********************************************************************************
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* *
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* Multiplexing TDO and Tristate control *
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|
* *
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**********************************************************************************/
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wire TDOShifted;
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assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
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reg TDOMuxed;
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// Tristate control for P_TDO pin
|
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assign P_TDO = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
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|
|
|
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|
/**********************************************************************************
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* *
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|
* End: Multiplexing TDO and Tristate control *
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|
* *
|
|
**********************************************************************************/
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|
|
|
|
|
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/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
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| Line 1004... |
Line 992... |
end
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end
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end
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end
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end
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end
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|
|
|
/**********************************************************************************
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* *
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* Multiplexing TDO and Tristate control *
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|
* *
|
|
**********************************************************************************/
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wire TDOShifted;
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assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
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/**********************************************************************************
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* *
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* End: Multiplexing TDO and Tristate control *
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* *
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**********************************************************************************/
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|
|
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// This multiplexing can be expanded with number of user registers
|
// This multiplexing can be expanded with number of user registers
|
|
reg TDOMuxed;
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always @ (JTAG_IR or TDOShifted or TDOBypassed)
|
always @ (JTAG_IR or TDOShifted or TDOBypassed)
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begin
|
begin
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case(JTAG_IR)
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case(JTAG_IR)
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`IDCODE: // Reading ID code
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`IDCODE: // Reading ID code
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begin
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begin
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| Line 1020... |
Line 1024... |
end
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end
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`DEBUG: // Debug
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`DEBUG: // Debug
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begin
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begin
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TDOMuxed<=#Tp TDOShifted;
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TDOMuxed<=#Tp TDOShifted;
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end
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end
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// SAMPLE_PRELOAD: // Sampling/Preloading
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`SAMPLE_PRELOAD: // Sampling/Preloading
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// begin
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begin
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// TDOMuxed<=#Tp ExitFromBSCell[`BSLength-1];
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TDOMuxed<=#Tp BS_CHAIN_I;
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// end
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end
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// EXTEST: // External test
|
`EXTEST: // External test
|
// begin
|
begin
|
// TDOMuxed<=#Tp ExitFromBSCell[`BSLength-1];
|
TDOMuxed<=#Tp BS_CHAIN_I;
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// end
|
end
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default: // BYPASS instruction
|
default: // BYPASS instruction
|
begin
|
begin
|
TDOMuxed<=#Tp TDOBypassed;
|
TDOMuxed<=#Tp TDOBypassed;
|
end
|
end
|
endcase
|
endcase
|
end
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end
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|
|
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// Tristate control for P_TDO pin
|
|
assign P_TDO = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
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|
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/**********************************************************************************
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/**********************************************************************************
|
* *
|
* *
|
* End: Activating Instructions *
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* End: Activating Instructions *
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* *
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* *
|
| Line 1078... |
Line 1084... |
* Connecting Registers *
|
* Connecting Registers *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
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dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
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dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
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.Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(Mclk),
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.Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(Mclk),
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.Reset(PowerONReset)
|
.Reset(PowerONReset),
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`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
,
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
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.ContinMode(ContinMode), .TraceEnable(TraceEnable), .RecSelDepend(RecSelDepend),
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|
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
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.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
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.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
|
.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
|
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
|
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
|
.QualifOper(QualifOper), .RecordPC_Wp(RecordPC_Wp),
|
.QualifOper(QualifOper), .RecordPC(RecordPC),
|
.RecordLSEA_Wp(RecordLSEA_Wp), .RecordLDATA_Wp(RecordLDATA_Wp),
|
.RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
|
.RecordSDATA_Wp(RecordSDATA_Wp), .RecordReadSPR_Wp(RecordReadSPR_Wp),
|
.RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
|
.RecordWriteSPR_Wp(RecordWriteSPR_Wp), .RecordINSTR_Wp(RecordINSTR_Wp),
|
.RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
|
.RecordPC_Bp(RecordPC_Bp), .RecordLSEA_Bp(RecordLSEA_Bp),
|
.WpTriggerValid(WpTriggerValid),
|
.RecordLDATA_Bp(RecordLDATA_Bp), .RecordSDATA_Bp(RecordSDATA_Bp),
|
|
.RecordReadSPR_Bp(RecordReadSPR_Bp), .RecordWriteSPR_Bp(RecordWriteSPR_Bp),
|
|
.RecordINSTR_Bp(RecordINSTR_Bp), .WpTriggerValid(WpTriggerValid),
|
|
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
|
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
|
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
|
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
|
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
|
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
|
.IQualifValid(IQualifValid),
|
.IQualifValid(IQualifValid),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.S topOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.S topOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
`endif
|
`endif
|
|
.RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
|
|
|
);
|
);
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* End: Connecting Registers *
|
* End: Connecting Registers *
|
| Line 1184... |
Line 1188... |
* *
|
* *
|
* Connecting trace module *
|
* Connecting trace module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
dbg_trace dbgTrace1(.Wp(Wp), .Bp(Bp), .DataIn(DataIn), .OpSelect(OpSelect),
|
dbg_trace dbgTrace1(.Wp(Wp), .Bp(Bp), .DataIn(RISC_DATA_IN), .OpSelect(OpSelect),
|
.LsStatus(LsStatus), .IStatus(IStatus), .CpuStall(CpuStall),
|
.LsStatus(LsStatus), .IStatus(IStatus), .RiscStall(RiscStall_trace),
|
.Mclk(Mclk), .Reset(RESET), .TraceChain(TraceChain),
|
.Mclk(Mclk), .Reset(RESET), .TraceChain(TraceChain),
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
|
.RecSelDepend(RecSelDepend), .WpTrigger(WpTrigger),
|
.WpTrigger(WpTrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
.RecordPC_Wp(RecordPC_Wp), .RecordLSEA_Wp(RecordLSEA_Wp),
|
.RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
|
.RecordLDATA_Wp(RecordLDATA_Wp), .RecordSDATA_Wp(RecordSDATA_Wp),
|
.RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
|
.RecordReadSPR_Wp(RecordReadSPR_Wp), .RecordWriteSPR_Wp(RecordWriteSPR_Wp),
|
.RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
|
.RecordINSTR_Wp(RecordINSTR_Wp), .RecordPC_Bp(RecordPC_Bp),
|
.RecordINSTR(RecordINSTR),
|
.RecordLSEA_Bp(RecordLSEA_Bp), .RecordLDATA_Bp(RecordLDATA_Bp),
|
|
.RecordSDATA_Bp(RecordSDATA_Bp), .RecordReadSPR_Bp(RecordReadSPR_Bp),
|
|
.RecordWriteSPR_Bp(RecordWriteSPR_Bp), .RecordINSTR_Bp(RecordINSTR_Bp),
|
|
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
|
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
|
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
|
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
|
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
|
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
|
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
|
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
|
.ReadBuffer(ReadBuffer_Mclk),
|
.ReadBuffer(ReadBuffer_Mclk),
|
