| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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//
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// Revision 1.30 2003/08/28 13:55:22 simons
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// Revision 1.30 2003/08/28 13:55:22 simons
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// Three more chains added for cpu debug access.
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// Three more chains added for cpu debug access.
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//
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//
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// Revision 1.29 2003/07/31 12:19:49 simons
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// Revision 1.29 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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// Multiple cpu support added.
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| Line 669... |
Line 672... |
RISCAccessTck3 <=#Tp 1'b0;
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RISCAccessTck3 <=#Tp 1'b0;
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end
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end
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end
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end
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assign wb_adr_o = ADDR & {32{wb_cyc_o}};
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assign wb_adr_o = {ADDR[31:2] & {30{wb_cyc_o}}, 2'b0};
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assign wb_we_o = RW & wb_cyc_o;
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assign wb_we_o = RW & wb_cyc_o;
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assign wb_dat_o = DataOut & {32{wb_cyc_o}};
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assign wb_cab_o = 1'b0;
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assign wb_cab_o = 1'b0;
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reg [31:0] wb_dat_o;
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always @(wb_sel_o or wb_cyc_o or DataOut)
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begin
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if(wb_cyc_o)
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case (wb_sel_o)
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4'b0001: wb_dat_o = {24'hx, DataOut[7:0]};
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4'b0010: wb_dat_o = {16'hx, DataOut[7:0], 8'hx};
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4'b0100: wb_dat_o = {8'hx, DataOut[7:0], 16'hx};
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4'b1000: wb_dat_o = {DataOut[7:0], 24'hx};
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4'b0011: wb_dat_o = {16'hx, DataOut[15:0]};
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4'b1100: wb_dat_o = {DataOut[15:0], 16'hx};
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default: wb_dat_o = DataOut;
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endcase
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else
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wb_dat_o = 32'hx;
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end
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reg [3:0] wb_sel_o;
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reg [3:0] wb_sel_o;
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always @(ADDR[1:0] or wb_cntl_o or wb_cyc_o)
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always @(ADDR[1:0] or wb_cntl_o or wb_cyc_o)
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begin
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begin
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if(wb_cyc_o)
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if(wb_cyc_o)
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case (wb_cntl_o)
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case (wb_cntl_o)
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2'b00: wb_sel_o = 4'hf;
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2'b00: wb_sel_o = 4'hf;
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2'b01: wb_sel_o = ADDR[1] ? 4'h3 : 4'hc;
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2'b01: wb_sel_o = ADDR[1] ? 4'h3 : 4'hc;
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2'b10: wb_sel_o = ADDR[1] ? (ADDR[0] ? 4'h1 : 4'h2) : (ADDR[0] ? 4'h4 : 4'h8);
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2'b10: wb_sel_o = ADDR[1] ? (ADDR[0] ? 4'h1 : 4'h2) : (ADDR[0] ? 4'h4 : 4'h8);
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default: wb_sel_o = 4'hf;
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default: wb_sel_o = 4'hx;
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endcase
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endcase
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else
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else
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wb_sel_o = 4'hf;
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wb_sel_o = 4'hx;
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end
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end
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// Synchronizing the RegAccess signal to risc_clk_i clock
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// Synchronizing the RegAccess signal to risc_clk_i clock
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dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
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dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
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.set2(RegAccessTck), .sync_out(RegAccess)
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.set2(RegAccessTck), .sync_out(RegAccess)
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| Line 787... |
Line 806... |
begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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WBReadLatch[31:0]<=#Tp 32'h0;
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WBReadLatch[31:0]<=#Tp 32'h0;
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else
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else
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if(wb_ack_i)
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if(wb_ack_i)
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WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
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case (wb_sel_o)
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4'b0001: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[7:0]};
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4'b0010: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[15:8]};
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4'b0100: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[23:16]};
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4'b1000: WBReadLatch[31:0]<=#Tp {24'h0, wb_dat_i[31:24]};
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4'b0011: WBReadLatch[31:0]<=#Tp {16'h0, wb_dat_i[15:0]};
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4'b1100: WBReadLatch[31:0]<=#Tp {16'h0, wb_dat_i[31:16]};
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default: WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
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endcase
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end
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end
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// Latching WISHBONE error cycle
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// Latching WISHBONE error cycle
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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