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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Small fix.
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//
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// Revision 1.1 2003/12/23 15:09:04 mohor
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// Revision 1.1 2003/12/23 15:09:04 mohor
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// New directory structure. New version of the debug interface.
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// New directory structure. New version of the debug interface.
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//
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//
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//
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//
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//
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//
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| Line 191... |
Line 194... |
reg address_unaligned;
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reg address_unaligned;
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reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_timeout, wb_timeout_sync, wb_timeout_tck;
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reg wb_timeout, wb_timeout_sync, wb_timeout_tck;
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reg busy_wb;
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reg busy_tck;
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reg wb_end;
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reg wb_end_rst;
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reg wb_end_rst_sync;
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reg wb_end_sync;
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reg wb_end_tck;
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reg busy_sync;
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reg [799:0] TDO_WISHBONE;
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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status <= #1 'h0;
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status <= #1 'h0;
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else if(crc_cnt_end & (~crc_cnt_end_q))
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else if(crc_cnt_end & (~crc_cnt_end_q))
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begin
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begin
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if (dr[2:0] == `WB_STATUS)
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if (dr[2:0] == `WB_STATUS)
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status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, address_unaligned};
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status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, busy_tck};
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else // Status is not updated when status read is requested
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else
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status <= #1 {crc_match_i, 2'b10, address_unaligned};
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status <= #1 {crc_match_i, 2'b10, address_unaligned};
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end
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end
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else if (shift_dr_i & (~status_cnt_end))
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else if (shift_dr_i & (~status_cnt_end))
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status <= #1 {status[0], status[`STATUS_LEN -1:1]};
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status <= #1 {status[0], status[`STATUS_LEN -1:1]};
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end
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end
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// Following status is shifted out:
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// Following status is shifted out after each command except WB_STATUS:
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// 1. bit: 1 if crc is OK, else 0
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// 1. bit: 1 if crc is OK, else 0
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// 2. bit: 1 if address is unaligned, else 0
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// 2. bit: 1 if address is unaligned, else 0
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// 3. bit: always 0
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// 3. bit: always 0
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// 4. bit: always 1
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// 4. bit: always 1
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// Following status is shifted out:
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// Following status is shifted out after WB_STATUS:
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// 1. bit: 1 if crc is OK, else 0
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// 1. bit: 1 if crc is OK, else 0
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// 2. bit: 1 if address is unaligned, else 0
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// 2. bit: 1 while WB access is in progress (busy_tck), else 0
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// 3. bit: 1 if WB timeout occured, else 0
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// 3. bit: 1 if WB timeout occured, else 0
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// 4. bit: 1 if WB error occured, else 0
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// 4. bit: 1 if WB error occured, else 0
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reg busy_wb;
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reg busy_tck;
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reg wb_ack_latched;
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reg wb_ack_latched_rst;
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reg wb_ack_latched_rst_sync;
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reg tck_ack_sync;
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reg tck_ack;
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reg busy_sync;
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reg [799:0] TDO_WISHBONE;
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always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
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always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
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begin
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begin
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if (pause_dr_i)
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if (pause_dr_i)
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begin
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begin
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| Line 360... |
Line 363... |
assign wb_cab_o = 1'b0;
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assign wb_cab_o = 1'b0;
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assign wb_stb_o = wb_cyc_o;
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assign wb_stb_o = wb_cyc_o;
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assign wb_cti_o = 3'h0; // always performing single access
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assign wb_cti_o = 3'h0; // always performing single access
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assign wb_bte_o = 2'h0; // always performing single access
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assign wb_bte_o = 2'h0; // always performing single access
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reg [31:0] input_storage;
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reg [31:0] input_data;
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i)
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begin
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begin
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if(wb_ack_i)
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if(wb_ack_i)
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input_storage <= #1 wb_dat_i;
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input_data <= #1 wb_dat_i;
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end
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end
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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wb_ack_latched <= #1 1'b0;
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wb_end <= #1 1'b0;
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else if (wb_ack_i)
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else if (wb_ack_i | wb_err_i | acc_cnt_limit)
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wb_ack_latched <= #1 1'b1;
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wb_end <= #1 1'b1;
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else if (wb_ack_latched_rst)
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else if (wb_end_rst)
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wb_ack_latched <= #1 1'b0;
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wb_end <= #1 1'b0;
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end
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end
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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begin
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begin
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tck_ack_sync <= #1 1'b0;
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wb_end_sync <= #1 1'b0;
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tck_ack <= #1 1'b0;
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wb_end_tck <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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tck_ack_sync <= #1 wb_ack_latched;
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wb_end_sync <= #1 wb_end;
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tck_ack <= #1 tck_ack_sync;
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wb_end_tck <= #1 wb_end_sync;
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end
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end
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end
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end
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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busy_wb <= #1 1'b0;
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busy_wb <= #1 1'b0;
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else if (wb_ack_latched_rst | wb_err_i | acc_cnt_limit)
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else if (wb_end_rst)
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busy_wb <= #1 1'b0;
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busy_wb <= #1 1'b0;
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else if (wb_cyc_o)
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else if (wb_cyc_o)
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busy_wb <= #1 1'b1;
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busy_wb <= #1 1'b1;
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end
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end
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| Line 424... |
Line 427... |
end
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end
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i)
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begin
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begin
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wb_ack_latched_rst_sync <= #1 tck_ack;
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wb_end_rst_sync <= #1 wb_end_tck;
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wb_ack_latched_rst <= #1 wb_ack_latched_rst_sync;
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wb_end_rst <= #1 wb_end_rst_sync;
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end
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end
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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