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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/12/23 16:22:46 mohor
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// Tmp version.
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//
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Small fix.
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// Small fix.
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//
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//
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// Revision 1.1 2003/12/23 15:09:04 mohor
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// Revision 1.1 2003/12/23 15:09:04 mohor
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// New directory structure. New version of the debug interface.
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// New directory structure. New version of the debug interface.
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| Line 124... |
Line 127... |
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reg tdo_o;
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reg tdo_o;
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reg [`WB_DR_LEN -1:0] dr;
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reg [`WB_DR_LEN -1:0] dr;
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wire enable;
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wire enable;
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reg [5:0] cnt;
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reg [1:0] cmd_cnt;
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reg [5:0] data_cnt;
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reg [5:0] crc_cnt;
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reg [5:0] crc_cnt;
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wire cnt_end;
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wire cmd_cnt_end;
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wire data_cnt_end;
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wire crc_cnt_end;
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wire crc_cnt_end;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q;
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reg status_reset_en;
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reg [`STATUS_CNT -1:0] status_cnt;
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reg [`STATUS_CNT -1:0] status_cnt;
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wire status_cnt_end;
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wire status_cnt_end;
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| Line 140... |
Line 146... |
assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC
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assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (enable & (~cnt_end))
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if (enable & (~data_cnt_end))
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dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
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dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
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end
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end
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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cnt <= #1 'h0;
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cmd_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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cnt <= #1 'h0;
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cmd_cnt <= #1 'h0;
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else if (enable & (~cnt_end))
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else if (enable & (~cmd_cnt_end))
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cnt <= #1 cnt + 1'b1;
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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end
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end
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assign cnt_end = cnt == `WB_DR_LEN;
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always @ (posedge tck_i or posedge trst_i)
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begin
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if (trst_i)
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data_cnt <= #1 'h0;
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else if (update_dr_i)
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data_cnt <= #1 'h0;
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else if (enable & cmd_cnt_end & (~data_cnt_end))
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data_cnt <= #1 data_cnt + 1'b1;
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end
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// crc counter
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// crc counter
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 'h0;
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else if(enable & cnt_end & (~crc_cnt_end))
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else if(enable & data_cnt_end & (~crc_cnt_end))
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crc_cnt <= #1 crc_cnt + 1'b1;
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crc_cnt <= #1 crc_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 'h0;
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end
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end
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign data_cnt_end = data_cnt == 6'd48;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_end = crc_cnt == 6'd32;
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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crc_cnt_end_q <= #1 crc_cnt_end;
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crc_cnt_end_q <= #1 crc_cnt_end;
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| Line 243... |
Line 260... |
else if (crc_cnt_end & (~crc_cnt_end_q))
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else if (crc_cnt_end & (~crc_cnt_end_q))
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begin
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begin
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tdo_o = crc_match_i;
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tdo_o = crc_match_i;
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TDO_WISHBONE = "crc_match_i";
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TDO_WISHBONE = "crc_match_i";
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end
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end
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else
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else if (crc_cnt_end)
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begin
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begin
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tdo_o = status[0];
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tdo_o = status[0];
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TDO_WISHBONE = "status";
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TDO_WISHBONE = "status";
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end
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end
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else
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begin
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tdo_o = 1'b0;
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TDO_WISHBONE = "zero while CRC is shifted in";
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end
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end
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end
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assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
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assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
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reg [2:0] cmd;
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reg [2:0] cmd, cmd_old;
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reg [31:0] adr;
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reg [31:0] adr;
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reg [15:0] len;
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reg [15:0] len;
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reg start_tck;
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reg start_tck;
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reg start_sync1;
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reg start_sync1;
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reg start_wb;
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reg start_wb;
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| Line 265... |
Line 287... |
always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
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if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
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begin
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begin
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cmd <= #1 dr[2:0];
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cmd <= #1 dr[2:0];
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cmd_old <= #1 cmd;
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adr <= #1 dr[34:3];
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adr <= #1 dr[34:3];
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len <= #1 dr[50:35];
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len <= #1 dr[50:35];
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start_tck <= #1 1'b1;
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start_tck <= #1 1'b1;
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end
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end
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else
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else
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| Line 298... |
Line 321... |
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i)
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begin
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begin
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// if (start_wb & (~start_wb_q) & (cmd > `WB_STATUS) & (cmd < `WB_GO)) // Setting starting address
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if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
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if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
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wb_adr_o <= #1 adr;
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wb_adr_o <= #1 adr;
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else if (wb_ack_i)
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else if (wb_ack_i)
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begin
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begin
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if ((cmd == `WB_WRITE8) | (cmd == `WB_READ8))
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if ((cmd == `WB_WRITE8) | (cmd == `WB_READ8))
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| Line 438... |
Line 460... |
begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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wb_error <= #1 1'b0;
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wb_error <= #1 1'b0;
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else if(wb_err_i)
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else if(wb_err_i)
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wb_error <= #1 1'b1;
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wb_error <= #1 1'b1;
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else if(wb_ack_i | acc_cnt_limit)
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else if((wb_ack_i | acc_cnt_limit) & status_reset_en) // error remains active until STATUS read is performed
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wb_error <= #1 1'b0;
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wb_error <= #1 1'b0;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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| Line 455... |
Line 477... |
begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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wb_timeout <= #1 1'b0;
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wb_timeout <= #1 1'b0;
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else if(acc_cnt_limit)
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else if(acc_cnt_limit)
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wb_timeout <= #1 1'b1;
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wb_timeout <= #1 1'b1;
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else if(wb_ack_i | wb_err_i)
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else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
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wb_timeout <= #1 1'b0;
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wb_timeout <= #1 1'b0;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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wb_timeout_sync <= #1 wb_timeout;
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wb_timeout_sync <= #1 wb_timeout;
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wb_timeout_tck <= #1 wb_timeout_sync;
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wb_timeout_tck <= #1 wb_timeout_sync;
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end
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end
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// wb_timeout and wb_error are locked until WB_STATUS is performed
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always @ (posedge tck_i or posedge trst_i)
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begin
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if (trst_i)
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status_reset_en <= 1'b0;
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else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
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status_reset_en <= #1 1'b1;
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else
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status_reset_en <= #1 1'b0;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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