| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.4 2004/01/05 12:16:00 mohor
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// tmp2 version.
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//
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// Revision 1.3 2003/12/23 16:22:46 mohor
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// Revision 1.3 2003/12/23 16:22:46 mohor
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// Tmp version.
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// Tmp version.
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//
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//
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Revision 1.2 2003/12/23 15:26:26 mohor
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// Small fix.
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// Small fix.
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| Line 121... |
Line 124... |
output [2:0] wb_cti_o;
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output [2:0] wb_cti_o;
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output [1:0] wb_bte_o;
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output [1:0] wb_bte_o;
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|
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reg wb_cyc_o;
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reg wb_cyc_o;
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reg [31:0] wb_adr_o;
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reg [31:0] wb_adr_o;
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reg [31:0] wb_dat_o;
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reg [3:0] wb_sel_o;
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reg [3:0] wb_sel_o;
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reg tdo_o;
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reg tdo_o;
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reg [`WB_DR_LEN -1:0] dr;
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reg [50:0] dr;
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wire enable;
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wire enable;
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reg [1:0] cmd_cnt;
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reg [1:0] cmd_cnt;
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reg [5:0] data_cnt;
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reg [5:0] crc_cnt;
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wire cmd_cnt_end;
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wire cmd_cnt_end;
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wire data_cnt_end;
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reg cmd_cnt_end_q;
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reg [5:0] addr_len_cnt;
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reg [5:0] addr_len_cnt_limit;
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wire addr_len_cnt_end;
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reg [5:0] crc_cnt;
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wire crc_cnt_end;
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wire crc_cnt_end;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q;
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reg [18:0] data_cnt;
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reg [18:0] data_cnt_limit;
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wire data_cnt_end;
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reg status_reset_en;
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reg status_reset_en;
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reg [`STATUS_CNT -1:0] status_cnt;
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reg [`STATUS_CNT -1:0] status_cnt;
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// reg [31:0] data_tck;
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reg [2:0] cmd, cmd_old;
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reg [31:0] adr;
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reg [15:0] len;
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reg start_tck;
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reg start_sync1;
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reg start_wb;
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reg start_wb_q;
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wire status_cnt_end;
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wire status_cnt_end;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign enable = wishbone_ce_i & shift_dr_i;
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assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC
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assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (enable & (~data_cnt_end))
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// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end)))
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dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
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if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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dr <= #1 {dr[49:0], tdi_i};
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end
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end
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//always @ (posedge tck_i)
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//begin
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// if (enable & (data_cnt_end)) // Igor !!! perhaps not needed data_cnt_end
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// data_tck <= #1 {data_tck[30:0], tdi_i};
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//end
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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cmd_cnt <= #1 'h0;
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cmd_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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| Line 165... |
Line 194... |
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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addr_len_cnt <= #1 'h0;
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else if (update_dr_i)
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addr_len_cnt <= #1 'h0;
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else if (enable & cmd_cnt_end & (~addr_len_cnt_end))
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addr_len_cnt <= #1 addr_len_cnt + 1'b1;
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end
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always @ (posedge tck_i or posedge trst_i)
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begin
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if (trst_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 'h0;
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else if (enable & cmd_cnt_end & (~data_cnt_end))
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else if (enable & cmd_cnt_end & (~data_cnt_end))
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data_cnt <= #1 data_cnt + 1'b1;
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data_cnt <= #1 data_cnt + 1'b1;
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end
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end
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wire byte, half, long;
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reg byte_q, half_q, long_q;
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assign byte = data_cnt[2:0] == 3'h0;
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assign half = data_cnt[3:0] == 4'h0;
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assign long = data_cnt[4:0] == 5'h0;
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always @ (posedge tck_i)
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begin
|
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byte_q <= #1 byte;
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half_q <= #1 half;
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long_q <= #1 long;
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end
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reg cmd_write;
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reg cmd_read;
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reg cmd_go;
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//wire previous_cmd_read;
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wire previous_cmd_write;
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//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
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assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
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reg [2:0] cmd_new;
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always @ (posedge tck_i or posedge trst_i)
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begin
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if (trst_i)
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cmd_new <= #1 3'h0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_new <= #1 dr[2:0];
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end
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always @ (posedge tck_i)
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begin
|
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if (update_dr_i)
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cmd_read <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_read <= #1 (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
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end
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always @ (posedge tck_i)
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begin
|
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if (update_dr_i)
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cmd_write <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_write <= #1 (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
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end
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always @ (posedge tck_i)
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begin
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if (update_dr_i)
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cmd_go <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q))
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cmd_go <= #1 (dr[2:0] == `WB_GO);
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end
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always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q))
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begin
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// (current command is WB_STATUS or WB_GO)
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if ( (dr[2:0] == `WB_STATUS) | (dr[2:0] == `WB_GO) )
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addr_len_cnt_limit = 6'd0;
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// (current command is WB_WRITEx or WB_READx)
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else
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addr_len_cnt_limit = 6'd48;
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end
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end
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always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q))
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begin
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// (current command is WB_GO and previous command is WB_WRITEx)
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if ( (dr[2:0] == `WB_GO) & previous_cmd_write )
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data_cnt_limit = (len<<3);
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else
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data_cnt_limit = 19'h0;
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end
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end
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`define WB_STATUS 3'h0
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`define WB_WRITE8 3'h1
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`define WB_WRITE16 3'h2
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`define WB_WRITE32 3'h3
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`define WB_GO 3'h4
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`define WB_READ8 3'h5
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`define WB_READ16 3'h6
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`define WB_READ32 3'h7
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// crc counter
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// crc counter
|
always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
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if (trst_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
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else if(enable & data_cnt_end & (~crc_cnt_end))
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// else if(enable & addr_len_cnt_end & (~crc_cnt_end))
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else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
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end
|
end
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|
|
assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign data_cnt_end = data_cnt == 6'd48;
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//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
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|
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign data_cnt_end = data_cnt == data_cnt_limit;
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|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
crc_cnt_end_q <= #1 crc_cnt_end;
|
crc_cnt_end_q <= #1 crc_cnt_end;
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|
cmd_cnt_end_q <= #1 cmd_cnt_end;
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end
|
end
|
|
|
// status counter
|
// status counter
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
| Line 206... |
Line 360... |
status_cnt <= #1 'h0;
|
status_cnt <= #1 'h0;
|
end
|
end
|
|
|
assign status_cnt_end = status_cnt == `STATUS_LEN;
|
assign status_cnt_end = status_cnt == `STATUS_LEN;
|
reg [`STATUS_LEN -1:0] status;
|
reg [`STATUS_LEN -1:0] status;
|
reg address_unaligned;
|
//reg address_unaligned;
|
|
|
reg wb_error, wb_error_sync, wb_error_tck;
|
reg wb_error, wb_error_sync, wb_error_tck;
|
reg wb_timeout, wb_timeout_sync, wb_timeout_tck;
|
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
|
|
|
reg busy_wb;
|
reg busy_wb;
|
reg busy_tck;
|
reg busy_tck;
|
reg wb_end;
|
reg wb_end;
|
reg wb_end_rst;
|
reg wb_end_rst;
|
| Line 226... |
Line 380... |
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
status <= #1 'h0;
|
status <= #1 'h0;
|
else if(crc_cnt_end & (~crc_cnt_end_q))
|
else if(crc_cnt_end & (~crc_cnt_end_q))
|
begin
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
if (dr[2:0] == `WB_STATUS)
|
|
status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, busy_tck};
|
|
else
|
|
status <= #1 {crc_match_i, 2'b10, address_unaligned};
|
|
end
|
|
else if (shift_dr_i & (~status_cnt_end))
|
else if (shift_dr_i & (~status_cnt_end))
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
end
|
end
|
// Following status is shifted out after each command except WB_STATUS:
|
// Following status is shifted out:
|
// 1. bit: 1 if crc is OK, else 0
|
|
// 2. bit: 1 if address is unaligned, else 0
|
|
// 3. bit: always 0
|
|
// 4. bit: always 1
|
|
|
|
// Following status is shifted out after WB_STATUS:
|
|
// 1. bit: 1 if crc is OK, else 0
|
// 1. bit: 1 if crc is OK, else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 3. bit: 1 if WB timeout occured, else 0
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 4. bit: 1 if WB error occured, else 0
|
// 4. bit: 1 if WB error occured, else 0
|
|
|
|
|
|
|
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
|
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
| Line 274... |
Line 418... |
end
|
end
|
end
|
end
|
|
|
assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
|
assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
|
|
|
reg [2:0] cmd, cmd_old;
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg [31:0] adr;
|
|
reg [15:0] len;
|
|
reg start_tck;
|
|
reg start_sync1;
|
|
reg start_wb;
|
|
reg start_wb_q;
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
|
if (cmd_write | cmd_read)
|
|
begin
|
|
cmd <= #1 dr[50:48];
|
|
adr <= #1 dr[47:16];
|
|
len <= #1 dr[15:0];
|
|
set_addr <= #1 1'b1;
|
|
end
|
|
else
|
|
begin
|
cmd <= #1 dr[2:0];
|
cmd <= #1 dr[2:0];
|
|
end
|
|
|
cmd_old <= #1 cmd;
|
cmd_old <= #1 cmd;
|
adr <= #1 dr[34:3];
|
end
|
len <= #1 dr[50:35];
|
else
|
|
set_addr <= #1 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if (cmd_go & previous_cmd_write)
|
|
begin
|
|
case (cmd) // synthesis parallel_case full_case
|
|
`WB_WRITE8 : begin
|
|
if (byte & (~byte_q))
|
|
begin
|
start_tck <= #1 1'b1;
|
start_tck <= #1 1'b1;
|
|
wb_dat_o <= #1 {4{dr[7:0]}};
|
|
end
|
|
else
|
|
begin
|
|
start_tck <= #1 1'b0;
|
|
end
|
|
end
|
|
`WB_WRITE16 : begin
|
|
if (half & (~half_q))
|
|
begin
|
|
start_tck <= #1 1'b1;
|
|
wb_dat_o <= #1 {2{dr[15:0]}};
|
|
end
|
|
else
|
|
begin
|
|
start_tck <= #1 1'b0;
|
|
end
|
|
end
|
|
`WB_WRITE32 : begin
|
|
if (long & (~long_q))
|
|
begin
|
|
start_tck <= #1 1'b1;
|
|
wb_dat_o <= #1 dr[31:0];
|
|
end
|
|
else
|
|
begin
|
|
start_tck <= #1 1'b0;
|
|
end
|
|
end
|
|
endcase
|
end
|
end
|
else
|
else
|
start_tck <= #1 1'b0;
|
start_tck <= #1 1'b0;
|
end
|
end
|
|
|
| Line 302... |
Line 493... |
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
start_sync1 <= #1 start_tck;
|
start_sync1 <= #1 start_tck;
|
start_wb <= #1 start_sync1;
|
start_wb <= #1 start_sync1;
|
start_wb_q <= #1 start_wb;
|
start_wb_q <= #1 start_wb;
|
|
set_addr_sync <= #1 set_addr;
|
|
set_addr_wb <= #1 set_addr_sync;
|
|
set_addr_wb_q <= #1 set_addr_wb;
|
end
|
end
|
|
|
reg [7:0] acc_cnt;
|
|
wire acc_cnt_limit;
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
else if (start_wb & (~start_wb_q) & cmd[2]) // "read" or "go" command igor !!! tu pride se nekaj, ki starta vse naslednje accesse
|
else if (start_wb & (~start_wb_q))
|
wb_cyc_o <= #1 1'b1;
|
wb_cyc_o <= #1 1'b1;
|
else if (wb_ack_i | wb_err_i | acc_cnt_limit)
|
else if (wb_ack_i | wb_err_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
wb_adr_o <= #1 adr;
|
wb_adr_o <= #1 adr;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if ((cmd == `WB_WRITE8) | (cmd == `WB_READ8))
|
if ((cmd_new == `WB_WRITE8) | (cmd == `WB_READ8))
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
else if ((cmd == `WB_WRITE16) | (cmd == `WB_READ16))
|
else if ((cmd_new == `WB_WRITE16) | (cmd == `WB_READ16))
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
else
|
else
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (wb_adr_o or cmd)
|
// adr byte | short | long
|
begin
|
|
wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
|
(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
|
wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
|
wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
|
wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
|
|
end
|
|
// byte | short | long
|
|
// 0 1000 1100 1111
|
// 0 1000 1100 1111
|
// 1 0100 err err
|
// 1 0100 err err
|
// 2 0010 0011 err
|
// 2 0010 0011 err
|
// 3 0001 err err
|
// 3 0001 err err
|
|
|
|
|
always @ (dr)
|
|
begin
|
|
address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
|
|
end
|
|
|
|
`define WB_STATUS 3'h0 // 000
|
|
`define WB_WRITE8 3'h1 // 001
|
|
`define WB_WRITE16 3'h2 // 010
|
|
`define WB_WRITE32 3'h3 // 011
|
|
`define WB_GO 3'h4 // 100
|
|
`define WB_READ8 3'h5 // 101
|
|
`define WB_READ16 3'h6 // 110
|
|
`define WB_READ32 3'h7 // 111
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
acc_cnt<= #1 8'h0;
|
begin
|
else
|
wb_sel_o[3:0] <= #1 4'h0;
|
if(wb_ack_i | wb_err_i | acc_cnt_limit)
|
end
|
acc_cnt<= #1 8'h0;
|
|
else
|
else
|
if(wb_cyc_o)
|
begin
|
acc_cnt<= #1 acc_cnt + 1'b1;
|
wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
|
(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
|
wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
|
wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
end
|
end
|
|
end
|
|
|
|
|
|
|
|
|
|
/*
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
|
if (wb_rst_i)
|
|
wb_dat_o[31:0] <= #1 32'h0;
|
|
else if (start_wb & (~start_wb_q))
|
|
begin
|
|
if (cmd[1:0] == 2'd1) // 8-bit access
|
|
wb_dat_o[31:0] <= #1 {4{8'h0}};
|
|
else if (cmd[1:0] == 2'd2) // 16-bit access
|
|
wb_dat_o[31:0] <= #1 {2{16'h0}};
|
|
else
|
|
wb_dat_o[31:0] <= #1 32'h0; //32-bit access
|
|
end
|
|
end
|
|
*/
|
|
|
|
//always @ (wb_adr_o or cmd)
|
|
//begin
|
|
// wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
|
// (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
|
// wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
|
// wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
|
// wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
|
|
//end
|
|
|
|
|
|
|
|
// always @ (dr)
|
|
// begin
|
|
// address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
|
|
// end
|
|
|
assign acc_cnt_limit = acc_cnt==8'hff;
|
|
|
|
|
|
assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)
|
assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
| Line 399... |
Line 607... |
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_end <= #1 1'b0;
|
wb_end <= #1 1'b0;
|
else if (wb_ack_i | wb_err_i | acc_cnt_limit)
|
else if (wb_ack_i | wb_err_i)
|
wb_end <= #1 1'b1;
|
wb_end <= #1 1'b1;
|
else if (wb_end_rst)
|
else if (wb_end_rst)
|
wb_end <= #1 1'b0;
|
wb_end <= #1 1'b0;
|
end
|
end
|
|
|
| Line 460... |
Line 668... |
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
else if(wb_err_i)
|
else if(wb_err_i)
|
wb_error <= #1 1'b1;
|
wb_error <= #1 1'b1;
|
else if((wb_ack_i | acc_cnt_limit) & status_reset_en) // error remains active until STATUS read is performed
|
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
end
|
end
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
wb_error_sync <= #1 wb_error;
|
wb_error_sync <= #1 wb_error;
|
wb_error_tck <= #1 wb_error_sync;
|
wb_error_tck <= #1 wb_error_sync;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_timeout <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
else if(acc_cnt_limit)
|
else if(start_wb & (~start_wb_q) & wb_cyc_o)
|
wb_timeout <= #1 1'b1;
|
wb_overrun <= #1 1'b1;
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
wb_timeout <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
end
|
end
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
wb_timeout_sync <= #1 wb_timeout;
|
wb_overrun_sync <= #1 wb_overrun;
|
wb_timeout_tck <= #1 wb_timeout_sync;
|
wb_overrun_tck <= #1 wb_overrun_sync;
|
end
|
end
|
|
|
|
|
|
|
// wb_timeout and wb_error are locked until WB_STATUS is performed
|
|
|
|
|
|
|
// wb_error is locked until WB_STATUS is performed
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
status_reset_en <= 1'b0;
|
status_reset_en <= 1'b0;
|
else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
|
else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
|
status_reset_en <= #1 1'b1;
|
status_reset_en <= #1 1'b1;
|
else
|
else
|
status_reset_en <= #1 1'b0;
|
status_reset_en <= #1 1'b0;
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
