| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2004/01/08 17:53:36 mohor
|
|
// tmp version.
|
|
//
|
// Revision 1.6 2004/01/07 11:58:56 mohor
|
// Revision 1.6 2004/01/07 11:58:56 mohor
|
// temp4 version.
|
// temp4 version.
|
//
|
//
|
// Revision 1.5 2004/01/06 17:15:19 mohor
|
// Revision 1.5 2004/01/06 17:15:19 mohor
|
// temp3 version.
|
// temp3 version.
|
| Line 133... |
Line 136... |
reg wb_cyc_o;
|
reg wb_cyc_o;
|
reg [31:0] wb_adr_o;
|
reg [31:0] wb_adr_o;
|
reg [31:0] wb_dat_o;
|
reg [31:0] wb_dat_o;
|
reg [3:0] wb_sel_o;
|
reg [3:0] wb_sel_o;
|
|
|
reg [3:0] wb_sel_old;
|
|
reg tdo_o;
|
reg tdo_o;
|
|
|
reg [50:0] dr;
|
reg [50:0] dr;
|
wire enable;
|
wire enable;
|
wire cmd_cnt_en;
|
wire cmd_cnt_en;
|
| Line 159... |
Line 161... |
reg data_cnt_end_q;
|
reg data_cnt_end_q;
|
reg status_reset_en;
|
reg status_reset_en;
|
|
|
reg crc_match_reg;
|
reg crc_match_reg;
|
|
|
reg [2:0] cmd, cmd_old;
|
reg [2:0] cmd, cmd_old, dr_cmd_latched;
|
reg [31:0] adr;
|
reg [31:0] adr;
|
reg [15:0] len;
|
reg [15:0] len;
|
reg start_rd_tck;
|
reg start_rd_tck;
|
reg start_rd_sync1;
|
reg start_rd_sync1;
|
reg start_wb_rd;
|
reg start_wb_rd;
|
| Line 179... |
Line 181... |
|
|
wire status_cnt_end;
|
wire status_cnt_end;
|
|
|
wire byte, half, long;
|
wire byte, half, long;
|
reg byte_q, half_q, long_q;
|
reg byte_q, half_q, long_q;
|
wire cmd_read;
|
reg cmd_read;
|
wire cmd_write;
|
reg cmd_write;
|
wire cmd_go;
|
reg cmd_go;
|
wire cmd_old_read;
|
reg cmd_old_read;
|
|
|
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
|
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
|
|
|
|
|
assign enable = wishbone_ce_i & shift_dr_i;
|
assign enable = wishbone_ce_i & shift_dr_i;
|
| Line 206... |
Line 208... |
/* if (cmd_old_read & cmd_go)
|
/* if (cmd_old_read & cmd_go)
|
begin
|
begin
|
case (cmd_old) // synthesis parallel_case full_case
|
case (cmd_old) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
dr[31:24] <= #1 input_data[]; mama
|
dr[31:24] <= #1 input_data[];
|
else
|
else
|
dr <= #1 dr<<1;
|
dr <= #1 dr<<1;
|
end
|
end
|
`WB_READ16: begin
|
`WB_READ16: begin
|
if(half & (~half_q))
|
if(half & (~half_q))
|
| Line 283... |
Line 285... |
long_q <= #1 long;
|
long_q <= #1 long;
|
end
|
end
|
|
|
|
|
|
|
assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
|
//assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
|
assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
|
//assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
|
assign cmd_go = cmd == `WB_GO;
|
//assign cmd_go = cmd == `WB_GO;
|
assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
|
//assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
|
|
|
|
|
wire dr_read;
|
wire dr_read;
|
wire dr_write;
|
wire dr_write;
|
wire dr_go;
|
wire dr_go;
|
wire dr_status;
|
|
|
|
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
|
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
|
assign dr_go = dr[2:0] == `WB_GO;
|
assign dr_go = dr[2:0] == `WB_GO;
|
assign dr_status = dr[2:0] == `WB_STATUS;
|
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
dr_read_latched <= #1 1'b0;
|
|
else if (cmd_cnt_end & (~cmd_cnt_end_q))
|
|
dr_read_latched <= #1 dr_read;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i)
|
|
begin
|
begin
|
if (update_dr_i)
|
dr_cmd_latched = 3'h0;
|
|
dr_read_latched <= #1 1'b0;
|
dr_write_latched <= #1 1'b0;
|
dr_write_latched <= #1 1'b0;
|
else if (cmd_cnt_end & (~cmd_cnt_end_q))
|
|
dr_write_latched <= #1 dr_write;
|
|
end
|
|
|
|
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if (update_dr_i)
|
|
dr_go_latched <= #1 1'b0;
|
dr_go_latched <= #1 1'b0;
|
|
end
|
else if (cmd_cnt_end & (~cmd_cnt_end_q))
|
else if (cmd_cnt_end & (~cmd_cnt_end_q))
|
|
begin
|
|
dr_cmd_latched = dr[2:0];
|
|
dr_read_latched <= #1 dr_read;
|
|
dr_write_latched <= #1 dr_write;
|
dr_go_latched <= #1 dr_go;
|
dr_go_latched <= #1 dr_go;
|
end
|
end
|
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (cmd_cnt == 2'h2)
|
if (cmd_cnt == 2'h2)
|
| Line 501... |
Line 492... |
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
crc_match_reg <= #1 crc_match_i;
|
crc_match_reg <= #1 crc_match_i;
|
end
|
end
|
|
|
|
/*
|
|
always @ (posedge tck_i or posedge trst_i)
|
|
begin
|
|
if (trst_i)
|
|
begin
|
|
cmd <= #1 'h0;
|
|
cmd_old <= #1 'h0;
|
|
end
|
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
|
begin
|
|
if (dr_write_latched | dr_read_latched)
|
|
cmd <= #1 dr[50:48];
|
|
else
|
|
cmd <= #1 dr[2:0];
|
|
|
|
cmd_old <= #1 cmd;
|
|
end
|
|
end
|
|
*/
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge trst_i)
|
begin
|
begin
|
if (trst_i)
|
if (trst_i)
|
begin
|
begin
|
cmd <= #1 'h0;
|
cmd <= #1 'h0;
|
cmd_old <= #1 'h0;
|
cmd_old <= #1 'h0;
|
|
cmd_read <= #1 1'b0;
|
|
cmd_write <= #1 1'b0;
|
|
cmd_go <= #1 1'b0;
|
|
cmd_old_read <= #1 1'b0;
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
if (dr_write_latched | dr_read_latched)
|
cmd <= #1 dr_cmd_latched;
|
cmd <= #1 dr[50:48];
|
|
else
|
|
cmd <= #1 dr[2:0];
|
|
|
|
cmd_old <= #1 cmd;
|
cmd_old <= #1 cmd;
|
|
cmd_read <= #1 dr_read_latched;
|
|
cmd_write <= #1 dr_write_latched;
|
|
cmd_go <= #1 dr_go_latched;
|
|
cmd_old_read <= #1 cmd_read;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
| Line 540... |
Line 554... |
|
|
|
|
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (set_addr & dr_read_latched)
|
// if (set_addr & dr_read_latched)
|
|
if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
|
else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
|
begin
|
begin
|
case (cmd_old) // synthesis parallel_case full_case
|
case (cmd_old) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
| Line 674... |
Line 689... |
// 3 0001 err err
|
// 3 0001 err err
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
begin
|
|
wb_sel_o[3:0] <= #1 4'h0;
|
wb_sel_o[3:0] <= #1 4'h0;
|
end
|
else if (cmd_write & dr_go_latched | cmd_read) // write or first read
|
else
|
|
begin
|
begin
|
wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
end
|
end
|
end
|
else // read
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
|
begin
|
begin
|
if (wb_rst_i)
|
wb_sel_o[0] <= #1 (cmd_old[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
wb_sel_old <= #1 4'h0;
|
(cmd_old[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
else if (wb_ack_i)
|
wb_sel_o[1] <= #1 (cmd_old[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1] ^ cmd_old[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_old <= #1 wb_sel_o;
|
wb_sel_o[2] <= #1 (cmd_old[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
|
end
|
end
|
end
|
|
|
|
|
assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)
|
assign wb_we_o = cmd_write & dr_go_latched;
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
|
|
