| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2004/01/13 11:28:14 mohor
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// tmp version.
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//
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// Revision 1.9 2004/01/10 07:50:24 mohor
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// Revision 1.9 2004/01/10 07:50:24 mohor
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// temp version.
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// temp version.
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//
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//
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// Revision 1.8 2004/01/09 12:48:44 mohor
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// Revision 1.8 2004/01/09 12:48:44 mohor
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// tmp version.
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// tmp version.
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| Line 191... |
Line 194... |
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wire status_cnt_end;
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wire status_cnt_end;
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wire byte, half, long;
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wire byte, half, long;
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reg byte_q, half_q, long_q;
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reg byte_q, half_q, long_q;
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reg byte_q2, half_q2, long_q2;
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reg cmd_read;
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reg cmd_read;
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reg cmd_write;
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reg cmd_write;
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reg cmd_go;
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reg cmd_go;
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//reg cmd_old_read;
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//reg cmd_old_read;
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| Line 216... |
Line 220... |
reg [799:0] TDO_WISHBONE;
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reg [799:0] TDO_WISHBONE;
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reg [399:0] latching_data;
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reg [399:0] latching_data;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg read_cycle;
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reg read_cycle;
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reg write_cycle;
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reg [2:0] read_type;
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reg [2:0] read_type;
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wire [31:0] input_data;
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wire [31:0] input_data;
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wire len_eq_0;
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wire len_eq_0;
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wire crc_cnt_31;
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wire crc_cnt_31;
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| Line 302... |
Line 307... |
latching_data = "32 bit shifted";
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latching_data = "32 bit shifted";
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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// else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
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else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
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begin
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begin
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dr <= #1 {dr[49:0], tdi_i};
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dr <= #1 {dr[49:0], tdi_i};
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latching_data = "tdi shifted in";
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latching_data = "tdi shifted in";
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end
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end
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else
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latching_data = "nothing";
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end
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end
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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| Line 370... |
Line 378... |
// else
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// else
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// begin
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// begin
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byte_q <= #1 byte;
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byte_q <= #1 byte;
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half_q <= #1 half;
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half_q <= #1 half;
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long_q <= #1 long;
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long_q <= #1 long;
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byte_q2 <= #1 byte_q;
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half_q2 <= #1 half_q;
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long_q2 <= #1 long_q;
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// end
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// end
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end
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end
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| Line 417... |
Line 428... |
addr_len_cnt_limit = 6'd48;
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addr_len_cnt_limit = 6'd48;
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end
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end
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end
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end
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wire go_prelim;
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assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
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/*
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always @ (posedge tck_i)
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begin
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if (update_dr_i)
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data_cnt_limit = 19'h0;
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// else if (((cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) | // current command is WB_GO and previous command is WB_WRITEx)
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else if ( go_prelim & cmd_write | // current command is WB_GO and previous command is WB_WRITEx)
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crc_cnt_31 & dr_go_latched & cmd_read // current command is WB_GO and previous command is WB_READx)
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)
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data_cnt_limit = {len, 3'b000};
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end
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*/
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (update_dr_i)
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if (update_dr_i)
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data_cnt_limit = 19'h0;
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else if (((cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) | // current command is WB_GO and previous command is WB_WRITEx)
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(crc_cnt_31 & dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
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)
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data_cnt_limit = {len, 3'b000};
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data_cnt_limit = {len, 3'b000};
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end
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end
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assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
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//assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
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assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
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// crc counter
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// crc counter
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always @ (posedge tck_i or posedge trst_i)
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always @ (posedge tck_i or posedge trst_i)
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begin
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begin
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if (trst_i)
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if (trst_i)
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| Line 463... |
Line 487... |
begin
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begin
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if (trst_i)
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if (trst_i)
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status_cnt1 <= #1 1'b0;
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status_cnt1 <= #1 1'b0;
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else if (update_dr_i)
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else if (update_dr_i)
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status_cnt1 <= #1 1'b0;
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status_cnt1 <= #1 1'b0;
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// else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched |
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// else if (data_cnt_end & (~data_cnt_end_q) & read_cycle |
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle |
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// crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
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crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
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// )
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else if (data_cnt_end & read_cycle |
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crc_cnt_end & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
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)
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)
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status_cnt1 <= #1 1'b1;
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status_cnt1 <= #1 1'b1;
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end
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end
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| Line 547... |
Line 573... |
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
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else if (read_cycle & crc_cnt_end & (~data_cnt_end))
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begin
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begin
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tdo_o = dr[31];
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tdo_o = dr[31];
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TDO_WISHBONE = "read data";
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TDO_WISHBONE = "read data";
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end
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end
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle) // cmd is already updated
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else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
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begin
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begin
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tdo_o = crc_match_reg;
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tdo_o = crc_match_reg;
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TDO_WISHBONE = "crc_match_reg";
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TDO_WISHBONE = "crc_match_reg";
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end
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end
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else if (crc_cnt_end & data_cnt_end) // cmd is already updated
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else if (crc_cnt_end & data_cnt_end) // cmd is already updated
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| Line 652... |
Line 678... |
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// Start wishbone read cycle
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// Start wishbone read cycle
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go) // First read after cmd is entered igor !!! Add something to block too many accesses.
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if (cmd_read & go_prelim) // First read after cmd is entered
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start_rd_tck <= #1 1'b1;
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start_rd_tck <= #1 1'b1;
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else if (read_cycle & dr_go_latched & crc_cnt_end & (~crc_cnt_end_q) & (~len_eq_0)) // Second read after first data is latched igor !!! Add something to block too many accesses.
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else if (read_cycle & dr_go_latched & crc_cnt_end & (~crc_cnt_end_q) & (~len_eq_0)) // Second read after first data is latched
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start_rd_tck <= #1 1'b1;
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start_rd_tck <= #1 1'b1;
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else if (read_cycle & (~len_eq_0))
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else if (read_cycle & (~len_eq_0))
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begin
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begin
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case (read_type) // synthesis parallel_case full_case
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case (read_type) // synthesis parallel_case full_case
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`WB_READ8 : begin
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`WB_READ8 : begin
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| Line 688... |
Line 714... |
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (update_dr_i)
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if (update_dr_i)
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read_cycle <= #1 1'b0;
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read_cycle <= #1 1'b0;
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else if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
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// else if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
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else if (cmd_read & go_prelim)
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read_cycle <= #1 1'b1;
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read_cycle <= #1 1'b1;
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end
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end
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
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// if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
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if (cmd_read & go_prelim)
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read_type <= #1 cmd;
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read_type <= #1 cmd;
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end
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end
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always @ (posedge tck_i)
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begin
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if (update_dr_i)
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write_cycle <= #1 1'b0;
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// else if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_write & dr_go)
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else if (cmd_write & go_prelim)
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write_cycle <= #1 1'b1;
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end
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// Start wishbone write cycle
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// Start wishbone write cycle
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (dr_go_latched & cmd_write)
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if (dr_go_latched & cmd_write)
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begin
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begin
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case (cmd) // synthesis parallel_case full_case
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case (cmd) // synthesis parallel_case full_case
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`WB_WRITE8 : begin
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`WB_WRITE8 : begin
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if (byte & (~byte_q))
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if (byte_q & (~byte_q2))
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begin
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begin
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start_wr_tck <= #1 1'b1;
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start_wr_tck <= #1 1'b1;
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wb_dat_o <= #1 {4{dr[7:0]}};
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wb_dat_o <= #1 {4{dr[7:0]}};
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end
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end
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else
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else
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begin
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begin
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start_wr_tck <= #1 1'b0;
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start_wr_tck <= #1 1'b0;
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end
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end
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end
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end
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`WB_WRITE16 : begin
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`WB_WRITE16 : begin
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if (half & (~half_q))
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if (half_q & (~half_q2))
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begin
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begin
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start_wr_tck <= #1 1'b1;
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start_wr_tck <= #1 1'b1;
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wb_dat_o <= #1 {2{dr[15:0]}};
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wb_dat_o <= #1 {2{dr[15:0]}};
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end
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end
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else
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else
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begin
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begin
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start_wr_tck <= #1 1'b0;
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start_wr_tck <= #1 1'b0;
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end
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end
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end
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end
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`WB_WRITE32 : begin
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`WB_WRITE32 : begin
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if (long & (~long_q))
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if (long_q & (~long_q2))
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begin
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begin
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start_wr_tck <= #1 1'b1;
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start_wr_tck <= #1 1'b1;
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wb_dat_o <= #1 dr[31:0];
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wb_dat_o <= #1 dr[31:0];
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end
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end
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else
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else
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