| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.11 2004/01/14 12:29:40 mohor
|
|
// temp version. Resets will be changed in next version.
|
|
//
|
// Revision 1.10 2004/01/13 11:28:14 mohor
|
// Revision 1.10 2004/01/13 11:28:14 mohor
|
// tmp version.
|
// tmp version.
|
//
|
//
|
// Revision 1.9 2004/01/10 07:50:24 mohor
|
// Revision 1.9 2004/01/10 07:50:24 mohor
|
// temp version.
|
// temp version.
|
| Line 82... |
Line 85... |
`include "dbg_wb_defines.v"
|
`include "dbg_wb_defines.v"
|
|
|
// Top module
|
// Top module
|
module dbg_wb(
|
module dbg_wb(
|
// JTAG signals
|
// JTAG signals
|
trst_i, // trst_i is active high (inverted on higher layers)
|
|
tck_i,
|
tck_i,
|
tdi_i,
|
tdi_i,
|
tdo_o,
|
tdo_o,
|
|
|
// TAP states
|
// TAP states
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| Line 96... |
Line 98... |
|
|
wishbone_ce_i,
|
wishbone_ce_i,
|
crc_match_i,
|
crc_match_i,
|
crc_en_o,
|
crc_en_o,
|
shift_crc_o,
|
shift_crc_o,
|
|
rst_i,
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
wb_rst_i, wb_clk_i,
|
wb_clk_i,
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
|
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
|
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
|
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
|
|
|
);
|
);
|
|
|
// JTAG signals
|
// JTAG signals
|
input trst_i;
|
|
input tck_i;
|
input tck_i;
|
input tdi_i;
|
input tdi_i;
|
output tdo_o;
|
output tdo_o;
|
|
|
// TAP states
|
// TAP states
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| Line 121... |
Line 123... |
|
|
input wishbone_ce_i;
|
input wishbone_ce_i;
|
input crc_match_i;
|
input crc_match_i;
|
output crc_en_o;
|
output crc_en_o;
|
output shift_crc_o;
|
output shift_crc_o;
|
|
input rst_i;
|
// WISHBONE common signals
|
// WISHBONE common signals
|
input wb_rst_i; // WISHBONE reset
|
|
input wb_clk_i; // WISHBONE clock
|
input wb_clk_i; // WISHBONE clock
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
output [31:0] wb_adr_o;
|
output [31:0] wb_adr_o;
|
output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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| Line 198... |
Line 199... |
reg byte_q, half_q, long_q;
|
reg byte_q, half_q, long_q;
|
reg byte_q2, half_q2, long_q2;
|
reg byte_q2, half_q2, long_q2;
|
reg cmd_read;
|
reg cmd_read;
|
reg cmd_write;
|
reg cmd_write;
|
reg cmd_go;
|
reg cmd_go;
|
//reg cmd_old_read;
|
|
|
|
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
|
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
|
|
|
reg [`STATUS_LEN -1:0] status;
|
reg [`STATUS_LEN -1:0] status;
|
|
|
| Line 221... |
Line 221... |
reg [399:0] latching_data;
|
reg [399:0] latching_data;
|
|
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg read_cycle;
|
reg read_cycle;
|
reg write_cycle;
|
reg write_cycle;
|
reg [2:0] read_type;
|
reg [2:0] rw_type;
|
wire [31:0] input_data;
|
wire [31:0] input_data;
|
|
|
wire len_eq_0;
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wire len_eq_0;
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wire crc_cnt_31;
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wire crc_cnt_31;
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|
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| Line 233... |
Line 233... |
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
|
|
reg [1:0] ptr;
|
reg [1:0] ptr;
|
|
|
//always @ (posedge tck_i)
|
|
//begin
|
|
// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
|
|
// dr <= #1 {dr[49:0], tdi_i};
|
|
//end
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
ptr <= #1 2'h0;
|
ptr <= #1 2'h0;
|
else if (read_cycle & dr_go_latched & crc_cnt_31) // first latch
|
else if (read_cycle & crc_cnt_31) // first latch
|
ptr <= #1 ptr + 1'b1;
|
ptr <= #1 ptr + 1'b1;
|
else if (read_cycle & cmd_go & byte & (~byte_q))
|
else if (read_cycle & byte & (~byte_q))
|
ptr <= ptr + 1'd1;
|
ptr <= ptr + 1'd1;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (read_cycle & dr_go_latched & crc_cnt_31)
|
if (read_cycle & crc_cnt_31)
|
begin
|
begin
|
dr[31:0] <= #1 input_data[31:0];
|
dr[31:0] <= #1 input_data[31:0];
|
latching_data = "First latch";
|
latching_data = "First latch";
|
end
|
end
|
else if (read_cycle & crc_cnt_end)
|
else if (read_cycle & crc_cnt_end)
|
begin
|
begin
|
case (read_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
begin
|
begin
|
case (ptr) // synthesis parallel_case
|
case (ptr) // synthesis parallel_case
|
2'b00 : dr[31:24] <= #1 input_data[31:24];
|
2'b00 : dr[31:24] <= #1 input_data[31:24];
|
| Line 307... |
Line 302... |
latching_data = "32 bit shifted";
|
latching_data = "32 bit shifted";
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
// else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
|
|
else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
|
else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
|
begin
|
begin
|
dr <= #1 {dr[49:0], tdi_i};
|
dr <= #1 {dr[49:0], tdi_i};
|
latching_data = "tdi shifted in";
|
latching_data = "tdi shifted in";
|
end
|
end
|
| Line 320... |
Line 314... |
end
|
end
|
|
|
|
|
assign cmd_cnt_en = enable & (~cmd_cnt_end);
|
assign cmd_cnt_en = enable & (~cmd_cnt_end);
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
cmd_cnt <= #1 'h0;
|
cmd_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
cmd_cnt <= #1 'h0;
|
cmd_cnt <= #1 'h0;
|
else if (cmd_cnt_en)
|
else if (cmd_cnt_en)
|
cmd_cnt <= #1 cmd_cnt + 1'b1;
|
cmd_cnt <= #1 cmd_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
|
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
addr_len_cnt <= #1 'h0;
|
addr_len_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
addr_len_cnt <= #1 'h0;
|
addr_len_cnt <= #1 'h0;
|
else if (addr_len_cnt_en)
|
else if (addr_len_cnt_en)
|
addr_len_cnt <= #1 addr_len_cnt + 1'b1;
|
addr_len_cnt <= #1 addr_len_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
assign data_cnt_en = enable & cmd_cnt_end & (~data_cnt_end);
|
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 'h0;
|
// else if (crc_cnt_31 & dr_go_latched & cmd_read)
|
|
// data_cnt <= #1 'h1;
|
|
else if (data_cnt_en)
|
else if (data_cnt_en)
|
data_cnt <= #1 data_cnt + 1'b1;
|
data_cnt <= #1 data_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
| Line 367... |
Line 359... |
assign long = data_cnt[4:0] == 5'd31;
|
assign long = data_cnt[4:0] == 5'd31;
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
// if (crc_cnt == 6'd31) // Reset to zero after crc to load first data byte. igor !!! This is probably not necessary
|
|
// begin
|
|
// byte_q <= #1 1'b0;
|
|
// half_q <= #1 1'b0;
|
|
// long_q <= #1 1'b0;
|
|
// end
|
|
// else
|
|
// begin
|
|
byte_q <= #1 byte;
|
byte_q <= #1 byte;
|
half_q <= #1 half;
|
half_q <= #1 half;
|
long_q <= #1 long;
|
long_q <= #1 long;
|
byte_q2 <= #1 byte_q;
|
byte_q2 <= #1 byte_q;
|
half_q2 <= #1 half_q;
|
half_q2 <= #1 half_q;
|
long_q2 <= #1 long_q;
|
long_q2 <= #1 long_q;
|
// end
|
|
end
|
end
|
|
|
|
|
|
|
//assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
|
|
//assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
|
|
//assign cmd_go = cmd == `WB_GO;
|
|
//assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
|
|
|
|
|
|
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
|
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
|
assign dr_go = dr[2:0] == `WB_GO;
|
assign dr_go = dr[2:0] == `WB_GO;
|
|
|
|
|
| Line 432... |
Line 408... |
|
|
wire go_prelim;
|
wire go_prelim;
|
|
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
|
|
|
/*
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if (update_dr_i)
|
|
data_cnt_limit = 19'h0;
|
|
// else if (((cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) | // current command is WB_GO and previous command is WB_WRITEx)
|
|
else if ( go_prelim & cmd_write | // current command is WB_GO and previous command is WB_WRITEx)
|
|
crc_cnt_31 & dr_go_latched & cmd_read // current command is WB_GO and previous command is WB_READx)
|
|
)
|
|
data_cnt_limit = {len, 3'b000};
|
|
end
|
|
*/
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
data_cnt_limit = {len, 3'b000};
|
data_cnt_limit = {len, 3'b000};
|
end
|
end
|
|
|
|
|
//assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
|
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
|
|
|
// crc counter
|
// crc counter
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
|
else if(crc_cnt_en)
|
else if(crc_cnt_en)
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
|
| Line 481... |
Line 444... |
data_cnt_end_q <= #1 data_cnt_end;
|
data_cnt_end_q <= #1 data_cnt_end;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
status_cnt1 <= #1 1'b0;
|
status_cnt1 <= #1 1'b0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
status_cnt1 <= #1 1'b0;
|
status_cnt1 <= #1 1'b0;
|
// else if (data_cnt_end & (~data_cnt_end_q) & read_cycle |
|
|
// crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
|
|
// )
|
|
else if (data_cnt_end & read_cycle |
|
else if (data_cnt_end & read_cycle |
|
crc_cnt_end & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
|
crc_cnt_end & (~read_cycle)
|
)
|
)
|
status_cnt1 <= #1 1'b1;
|
status_cnt1 <= #1 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
begin
|
begin
|
status_cnt2 <= #1 1'b0;
|
status_cnt2 <= #1 1'b0;
|
status_cnt3 <= #1 1'b0;
|
status_cnt3 <= #1 1'b0;
|
status_cnt4 <= #1 1'b0;
|
status_cnt4 <= #1 1'b0;
|
end
|
end
|
| Line 523... |
Line 483... |
|
|
|
|
assign status_cnt_end = status_cnt4;
|
assign status_cnt_end = status_cnt4;
|
|
|
reg [199:0] status_text;
|
reg [199:0] status_text;
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
begin
|
begin
|
status <= #1 'h0;
|
status <= #1 'h0;
|
status_text <= #1 "reset";
|
status_text <= #1 "reset";
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
| Line 553... |
Line 513... |
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 4. bit: 1 if WB error occured, else 0
|
// 4. bit: 1 if WB error occured, else 0
|
|
|
|
|
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or cmd_read or crc_match_i or
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or dr_go_latched or cmd_read or
|
data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr or cmd_go)
|
crc_match_i or data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or
|
|
dr or cmd_go)
|
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
TDO_WISHBONE = "busy_tck";
|
TDO_WISHBONE = "busy_tck";
|
end
|
end
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
TDO_WISHBONE = "crc_match_i";
|
TDO_WISHBONE = "crc_match_i";
|
end
|
end
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
| Line 598... |
Line 556... |
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
crc_match_reg <= #1 crc_match_i;
|
crc_match_reg <= #1 crc_match_i;
|
end
|
end
|
|
|
/*
|
|
always @ (posedge tck_i or posedge trst_i)
|
|
begin
|
|
if (trst_i)
|
|
begin
|
|
cmd <= #1 'h0;
|
|
cmd_old <= #1 'h0;
|
|
end
|
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
|
begin
|
|
if (dr_write_latched | dr_read_latched)
|
|
cmd <= #1 dr[50:48];
|
|
else
|
|
cmd <= #1 dr[2:0];
|
|
|
|
cmd_old <= #1 cmd;
|
|
end
|
|
end
|
|
*/
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
begin
|
begin
|
cmd <= #1 'h0;
|
cmd <= #1 'h0;
|
cmd_old <= #1 'h0;
|
cmd_old <= #1 'h0;
|
cmd_read <= #1 1'b0;
|
cmd_read <= #1 1'b0;
|
cmd_write <= #1 1'b0;
|
cmd_write <= #1 1'b0;
|
cmd_go <= #1 1'b0;
|
cmd_go <= #1 1'b0;
|
// cmd_old_read <= #1 1'b0;
|
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
cmd <= #1 dr_cmd_latched;
|
cmd <= #1 dr_cmd_latched;
|
cmd_old <= #1 cmd;
|
cmd_old <= #1 cmd;
|
cmd_read <= #1 dr_read_latched;
|
cmd_read <= #1 dr_read_latched;
|
cmd_write <= #1 dr_write_latched;
|
cmd_write <= #1 dr_write_latched;
|
cmd_go <= #1 dr_go_latched;
|
cmd_go <= #1 dr_go_latched;
|
// cmd_old_read <= #1 cmd_read;
|
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
| Line 660... |
Line 597... |
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
len <= #1 dr[15:0];
|
len <= #1 dr[15:0];
|
else if (wb_end_tck & (~wb_end_tck_q))
|
// else if (wb_end_tck & (~wb_end_tck_q))
|
|
else if (start_rd_tck)
|
begin
|
begin
|
case (read_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : len <= #1 len - 1'd1;
|
`WB_READ8 : len <= #1 len - 1'd1;
|
`WB_READ16: len <= #1 len - 2'd2;
|
`WB_READ16: len <= #1 len - 2'd2;
|
`WB_READ32: len <= #1 len - 3'd4;
|
`WB_READ32: len <= #1 len - 3'd4;
|
endcase
|
endcase
|
end
|
end
|
| Line 674... |
Line 612... |
|
|
|
|
assign len_eq_0 = len == 16'h0;
|
assign len_eq_0 = len == 16'h0;
|
|
|
|
|
|
|
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (cmd_read & go_prelim) // First read after cmd is entered
|
if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else if (read_cycle & dr_go_latched & crc_cnt_end & (~crc_cnt_end_q) & (~len_eq_0)) // Second read after first data is latched
|
else if (read_cycle & crc_cnt_31 & (~len_eq_0)) // Second read after first data is latched
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else if (read_cycle & (~len_eq_0))
|
else if (read_cycle & (~len_eq_0))
|
begin
|
begin
|
case (read_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
if(byte & (~byte_q))
|
if(byte & (~byte_q))
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else
|
else
|
start_rd_tck <= #1 1'b0;
|
start_rd_tck <= #1 1'b0;
|
| Line 714... |
Line 651... |
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
read_cycle <= #1 1'b0;
|
read_cycle <= #1 1'b0;
|
// else if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
|
|
else if (cmd_read & go_prelim)
|
else if (cmd_read & go_prelim)
|
read_cycle <= #1 1'b1;
|
read_cycle <= #1 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
// if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
|
if ((cmd_read | cmd_write) & go_prelim)
|
if (cmd_read & go_prelim)
|
rw_type <= #1 cmd;
|
read_type <= #1 cmd;
|
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
write_cycle <= #1 1'b0;
|
write_cycle <= #1 1'b0;
|
// else if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_write & dr_go)
|
|
else if (cmd_write & go_prelim)
|
else if (cmd_write & go_prelim)
|
write_cycle <= #1 1'b1;
|
write_cycle <= #1 1'b1;
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
// Start wishbone write cycle
|
// Start wishbone write cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (dr_go_latched & cmd_write)
|
if (write_cycle)
|
begin
|
begin
|
case (cmd) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_WRITE8 : begin
|
`WB_WRITE8 : begin
|
if (byte_q & (~byte_q2))
|
if (byte_q & (~byte_q2))
|
begin
|
begin
|
start_wr_tck <= #1 1'b1;
|
start_wr_tck <= #1 1'b1;
|
wb_dat_o <= #1 {4{dr[7:0]}};
|
wb_dat_o <= #1 {4{dr[7:0]}};
|
| Line 803... |
Line 734... |
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb_q <= #1 set_addr_wb;
|
set_addr_wb_q <= #1 set_addr_wb;
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (rst_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
|
else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
|
wb_cyc_o <= #1 1'b1;
|
wb_cyc_o <= #1 1'b1;
|
else if (wb_ack_i | wb_err_i)
|
else if (wb_ack_i | wb_err_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
| Line 821... |
Line 752... |
begin
|
begin
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
wb_adr_o <= #1 adr;
|
wb_adr_o <= #1 adr;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if ((cmd == `WB_WRITE8) | (read_type == `WB_READ8))
|
if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8))
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
else if ((cmd == `WB_WRITE16) | (read_type == `WB_READ16))
|
else if ((rw_type == `WB_WRITE16) | (rw_type == `WB_READ16))
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
else
|
else
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
end
|
end
|
end
|
end
|
| Line 838... |
Line 769... |
// 0 1000 1100 1111
|
// 0 1000 1100 1111
|
// 1 0100 err err
|
// 1 0100 err err
|
// 2 0010 0011 err
|
// 2 0010 0011 err
|
// 3 0001 err err
|
// 3 0001 err err
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (rst_i)
|
wb_sel_o[3:0] <= #1 4'h0;
|
wb_sel_o[3:0] <= #1 4'h0;
|
else if (cmd_write & dr_go_latched | cmd_read) // write or first read
|
else
|
begin
|
|
wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
|
(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
|
wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
|
|
wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
|
end
|
|
else // read
|
|
begin
|
begin
|
wb_sel_o[0] <= #1 (read_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (read_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
wb_sel_o[0] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
|
(read_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
(rw_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[1] <= #1 (read_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (read_type[1] ^ read_type[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[1] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1] ^ rw_type[0]) & (wb_adr_o[1:0] == 2'b10);
|
wb_sel_o[2] <= #1 (read_type[1]) & (wb_adr_o[1:0] == 2'b00) | (read_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[2] <= #1 (rw_type[1]) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
|
end
|
end
|
end
|
end
|
|
|
|
|
assign wb_we_o = cmd_write & dr_go_latched;
|
assign wb_we_o = write_cycle;
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (rst_i)
|
wb_end <= #1 1'b0;
|
wb_end <= #1 1'b0;
|
else if (wb_ack_i | wb_err_i)
|
else if (wb_ack_i | wb_err_i)
|
wb_end <= #1 1'b1;
|
wb_end <= #1 1'b1;
|
else if (wb_end_rst)
|
else if (wb_end_rst)
|
wb_end <= #1 1'b0;
|
wb_end <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
begin
|
begin
|
wb_end_sync <= #1 1'b0;
|
wb_end_sync <= #1 1'b0;
|
wb_end_tck <= #1 1'b0;
|
wb_end_tck <= #1 1'b0;
|
wb_end_tck_q<= #1 1'b0;
|
wb_end_tck_q<= #1 1'b0;
|
end
|
end
|
| Line 896... |
Line 819... |
wb_end_tck_q<= #1 wb_end_tck;
|
wb_end_tck_q<= #1 wb_end_tck;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (rst_i)
|
busy_wb <= #1 1'b0;
|
busy_wb <= #1 1'b0;
|
else if (wb_end_rst)
|
else if (wb_end_rst)
|
busy_wb <= #1 1'b0;
|
busy_wb <= #1 1'b0;
|
else if (wb_cyc_o)
|
else if (wb_cyc_o)
|
busy_wb <= #1 1'b1;
|
busy_wb <= #1 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
begin
|
begin
|
busy_sync <= #1 1'b0;
|
busy_sync <= #1 1'b0;
|
busy_tck <= #1 1'b0;
|
busy_tck <= #1 1'b0;
|
end
|
end
|
else
|
else
|
| Line 929... |
Line 852... |
wb_end_rst_sync <= #1 wb_end_tck;
|
wb_end_rst_sync <= #1 wb_end_tck;
|
wb_end_rst <= #1 wb_end_rst_sync;
|
wb_end_rst <= #1 wb_end_rst_sync;
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (rst_i)
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
else if(wb_err_i)
|
else if(wb_err_i)
|
wb_error <= #1 1'b1;
|
wb_error <= #1 1'b1;
|
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
| Line 947... |
Line 870... |
wb_error_tck <= #1 wb_error_sync;
|
wb_error_tck <= #1 wb_error_sync;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (rst_i)
|
wb_overrun <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
|
else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
|
wb_overrun <= #1 1'b1;
|
wb_overrun <= #1 1'b1;
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
|
wb_overrun <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
| Line 969... |
Line 892... |
|
|
|
|
|
|
|
|
// wb_error is locked until WB_STATUS is performed
|
// wb_error is locked until WB_STATUS is performed
|
always @ (posedge tck_i or posedge trst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (trst_i)
|
if (rst_i)
|
status_reset_en <= 1'b0;
|
status_reset_en <= 1'b0;
|
else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
|
else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
|
status_reset_en <= #1 1'b1;
|
status_reset_en <= #1 1'b1;
|
else
|
else
|
status_reset_en <= #1 1'b0;
|
status_reset_en <= #1 1'b0;
|
end
|
end
|
|
|
/*
|
|
to gre ven
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
|
wb_adr_o <= #1 adr;
|
|
else if (wb_ack_i)
|
|
begin
|
|
if (read_type == `WB_READ8)
|
|
wb_adr_o <= #1 wb_adr_o + 1'd1;
|
|
else if (read_type == `WB_READ16)
|
|
wb_adr_o <= #1 wb_adr_o + 2'd2;
|
|
else
|
|
wb_adr_o <= #1 wb_adr_o + 3'd4;
|
|
end
|
|
end
|
|
*/
|
|
reg [7:0] mem [0:3];
|
reg [7:0] mem [0:3];
|
reg [2:0] mem_ptr;
|
reg [2:0] mem_ptr;
|
reg wishbone_ce_sync;
|
reg wishbone_ce_sync;
|
reg wishbone_ce_rst;
|
reg wishbone_ce_rst;
|
|
|
| Line 1014... |
Line 921... |
begin
|
begin
|
if(wishbone_ce_rst)
|
if(wishbone_ce_rst)
|
mem_ptr <= #1 'h0;
|
mem_ptr <= #1 'h0;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if (read_type == `WB_READ8)
|
if (rw_type == `WB_READ8)
|
mem_ptr <= #1 mem_ptr + 1'd1;
|
mem_ptr <= #1 mem_ptr + 1'd1;
|
else if (read_type == `WB_READ16)
|
else if (rw_type == `WB_READ16)
|
mem_ptr <= #1 mem_ptr + 2'd2;
|
mem_ptr <= #1 mem_ptr + 2'd2;
|
end
|
end
|
end
|
end
|
|
|
|
|
