| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
|
//
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// CVS Revision History
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// CVS Revision History
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//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.30 2004/01/20 08:03:35 mohor
|
|
// IDCODE test improved.
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//
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// Revision 1.29 2004/01/19 13:13:18 mohor
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// Revision 1.29 2004/01/19 13:13:18 mohor
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// Define tap_defines.v added to test bench.
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// Define tap_defines.v added to test bench.
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//
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//
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// Revision 1.28 2004/01/19 12:38:10 mohor
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// Revision 1.28 2004/01/19 12:38:10 mohor
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// Waiting for "ready" improved.
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// Waiting for "ready" improved.
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| Line 221... |
Line 224... |
reg test_enabled;
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reg test_enabled;
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|
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reg [31:0] result;
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reg [31:0] result;
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reg [31:0] in_data_le, in_data_be;
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reg [31:0] in_data_le, in_data_be;
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reg [31:0] id;
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reg [31:0] id;
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reg crc_out_en;
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reg crc_out_shift;
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wire crc_out;
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reg crc_in_en;
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wire crc_match_in;
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wire crc_match_in;
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reg [31:0] crc_in;
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reg [31:0] crc_out;
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|
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wire tdo;
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wire tdo;
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assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
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assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
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| Line 319... |
Line 319... |
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);
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);
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|
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|
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// Connecting CRC module that calculates CRC that is shifted into debug
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dbg_crc32_d1 crc32_bench_out
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|
(
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.data (tdi_pad_i),
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.enable (crc_out_en),
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.shift (crc_out_shift),
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.rst (wb_rst_i),
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.sync_rst (update_dr_o),
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.crc_out (crc_out),
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.clk (tck_pad_i),
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.crc_match ()
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);
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|
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// Connecting CRC module that calculates CRC that is shifted from debug to bench
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dbg_crc32_d1 crc32_bench_in
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(
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|
.data (tdo),
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.enable (crc_in_en),
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.shift (1'b0),
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.rst (wb_rst_i),
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.sync_rst (update_dr_o),
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.crc_out (),
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.clk (tck_pad_i),
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.crc_match (crc_match_in)
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|
);
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wb_slave_behavioral wb_slave
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wb_slave_behavioral wb_slave
|
(
|
(
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.CLK_I (wb_clk_i),
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.CLK_I (wb_clk_i),
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.RST_I (wb_rst_i),
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.RST_I (wb_rst_i),
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.ACK_O (wb_ack_i),
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.ACK_O (wb_ack_i),
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| Line 395... |
Line 363... |
|
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// Initial values
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// Initial values
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initial
|
initial
|
begin
|
begin
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test_enabled = 1'b0;
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test_enabled = 1'b0;
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crc_out_en = 1'b0;
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crc_out_shift = 1'b0;
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crc_in_en = 1'b0;
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wb_data = 32'h01234567;
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wb_data = 32'h01234567;
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trst_pad_i = 1'b1;
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trst_pad_i = 1'b1;
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tms_pad_i = 1'hz;
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tms_pad_i = 1'hz;
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tck_pad_i = 1'hz;
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tck_pad_i = 1'hz;
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tdi_pad_i = 1'hz;
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tdi_pad_i = 1'hz;
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| Line 739... |
Line 704... |
tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1);
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gen_clk(1);
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(2); // we are in shiftDR
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gen_clk(2); // we are in shiftDR
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crc_out_en = 1; // Enable CRC calculation
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crc_out = 32'hffffffff; // Initialize outgoing CRC
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|
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tdi_pad_i<=#1 1'b1; // chain_select bit
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tdi_pad_i<=#1 1'b1; // chain_select bit
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|
calculate_crc(1'b1);
|
gen_clk(1);
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gen_clk(1);
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for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
|
for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
|
begin
|
begin
|
tdi_pad_i<=#1 data[i];
|
tdi_pad_i<=#1 data[i];
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calculate_crc(data[i]);
|
gen_clk(1);
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gen_clk(1);
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end
|
end
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crc_out_en = 0; // Disable CRC calculation
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crc_out_shift = 1; // Enable CRC shifting
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for(i=31; i>=0; i=i-1)
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for(i=31; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
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if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
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tdi_pad_i<=#1 ~crc_out; // error crc
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tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out; // ok crc
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tdi_pad_i<=#1 crc_out[i]; // ok crc
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|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
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crc_out_shift = 0; // Disable CRC shifting
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|
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tdi_pad_i<=#1 'hz; // tri-state
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tdi_pad_i<=#1 'hz; // tri-state
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|
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crc_in_en = 1; // Enable CRC calculation on incoming data
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crc_in = 32'hffffffff; // Initialize incoming CRC
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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for(i=0; i<`CRC_LEN -1; i=i+1)
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for(i=0; i<`CRC_LEN -1; i=i+1)
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gen_clk(1);
|
gen_clk(1);
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tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
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gen_clk(1); // to exit1_dr
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gen_clk(1); // to exit1_dr
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crc_in_en = 0; // Disable CRC calculation on incoming data
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|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
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|
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tdi_pad_i<=#1 'hz; // tri-state
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tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
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gen_clk(1); // to update_dr
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tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
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gen_clk(1); // to run_test_idle
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gen_clk(1); // to run_test_idle
|
end
|
end
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| Line 889... |
Line 847... |
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1);
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gen_clk(1);
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(2); // we are in shiftDR
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gen_clk(2); // we are in shiftDR
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crc_out_en = 1; // Enable CRC calculation
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crc_out = 32'hffffffff; // Initialize outgoing CRC
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|
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tdi_pad_i<=#1 1'b0; // chain_select bit = 0
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tdi_pad_i<=#1 1'b0; // chain_select bit = 0
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calculate_crc(1'b0);
|
gen_clk(1);
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gen_clk(1);
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|
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for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
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|
calculate_crc(command[i]);
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gen_clk(1);
|
gen_clk(1);
|
end
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end
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for(i=31; i>=0; i=i-1) // address
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for(i=31; i>=0; i=i-1) // address
|
begin
|
begin
|
tdi_pad_i<=#1 addr[i];
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tdi_pad_i<=#1 addr[i];
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calculate_crc(addr[i]);
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gen_clk(1);
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gen_clk(1);
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end
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end
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for(i=15; i>=0; i=i-1) // length
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for(i=15; i>=0; i=i-1) // length
|
begin
|
begin
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tdi_pad_i<=#1 length[i];
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tdi_pad_i<=#1 length[i];
|
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calculate_crc(length[i]);
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gen_clk(1);
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gen_clk(1);
|
end
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end
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|
|
crc_out_en = 0; // Disable CRC calculation
|
|
crc_out_shift = 1; // Enable CRC shifting
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|
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for(i=31; i>=0; i=i-1)
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for(i=31; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
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if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
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tdi_pad_i<=#1 ~crc_out; // error crc
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tdi_pad_i<=#1 ~crc_out[i]; // error crc
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else
|
else
|
tdi_pad_i<=#1 crc_out; // ok crc
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tdi_pad_i<=#1 crc_out[i]; // ok crc
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|
|
gen_clk(1);
|
gen_clk(1);
|
end
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end
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|
crc_out_shift = 0; // Disable CRC shifting
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|
|
|
tdi_pad_i<=#1 'hz;
|
tdi_pad_i<=#1 'hz;
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|
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crc_in_en = 1; // Enable CRC calculation on incoming data
|
crc_in = 32'hffffffff; // Initialize incoming CRC
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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|
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
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|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
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gen_clk(1); // to exit1_dr
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|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
|
| Line 971... |
Line 927... |
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out_en = 1; // Enable CRC calculation
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
|
|
calculate_crc(command[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
crc_out_en = 0; // Disable CRC calculation
|
|
crc_out_shift = 1; // Enable CRC shifting
|
|
|
|
for(i=31; i>=0; i=i-1)
|
for(i=31; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
tdi_pad_i<=#1 ~crc_out; // error crc
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
| Line 1011... |
Line 964... |
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
|
| Line 1043... |
Line 995... |
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out_en = 1; // Enable CRC calculation
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
|
|
calculate_crc(command[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
|
|
if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
| Line 1066... |
Line 1020... |
wb_data = wb_data + 32'h11111111;
|
wb_data = wb_data + 32'h11111111;
|
$display("\t\twb_data = 0x%x", wb_data);
|
$display("\t\twb_data = 0x%x", wb_data);
|
end
|
end
|
pointer = 31-i[4:0];
|
pointer = 31-i[4:0];
|
tdi_pad_i<=#1 wb_data[pointer];
|
tdi_pad_i<=#1 wb_data[pointer];
|
|
calculate_crc(wb_data[pointer]);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
end
|
end
|
end
|
end
|
|
|
crc_out_en = 0; // Disable CRC calculation
|
|
crc_out_shift = 1; // Enable CRC shifting
|
|
|
|
for(i=31; i>=1; i=i-1)
|
for(i=31; i>=1; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 crc_out; // ok crc
|
tdi_pad_i<=#1 crc_out[i];
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
if (gen_crc_err) // Generate crc error at last crc bit
|
if (gen_crc_err) // Generate crc error at last crc bit
|
tdi_pad_i<=#1 ~crc_out; // error crc
|
tdi_pad_i<=#1 ~crc_out[0]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out; // ok crc
|
tdi_pad_i<=#1 crc_out[0]; // ok crc
|
|
|
if (wait_for_wb_ready)
|
if (wait_for_wb_ready)
|
begin
|
begin
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
|
gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
|
crc_out_shift = 0; // Disable CRC shifting
|
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to pause_dr
|
gen_clk(1); // to pause_dr
|
|
|
#2; // wait a bit for tdo to activate
|
#2; // wait a bit for tdo to activate
|
while (tdo) // waiting for wb to send "ready"
|
while (tdo) // waiting for wb to send "ready"
|
| Line 1110... |
Line 1061... |
begin
|
begin
|
gen_clk(1); // Last CRC is shifted on this clk
|
gen_clk(1); // Last CRC is shifted on this clk
|
end
|
end
|
|
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
|
|
if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
begin
|
begin
|
$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
|
$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
|
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
|
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
|
| Line 1132... |
Line 1082... |
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
|
| Line 1237... |
Line 1186... |
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out_en = 1; // Enable CRC calculation
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
|
|
calculate_crc(command[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=31; i>=0; i=i-1) // address
|
for(i=31; i>=0; i=i-1) // address
|
begin
|
begin
|
tdi_pad_i<=#1 addr[i];
|
tdi_pad_i<=#1 addr[i];
|
|
calculate_crc(addr[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
crc_out_en = 0; // Disable CRC calculation
|
|
crc_out_shift = 1; // Enable CRC shifting
|
|
|
|
for(i=31; i>=0; i=i-1)
|
for(i=31; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
tdi_pad_i<=#1 ~crc_out; // error crc
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
|
tdi_pad_i<=#1 'hz;
|
tdi_pad_i<=#1 'hz;
|
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
|
| Line 1314... |
Line 1260... |
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1);
|
gen_clk(1);
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
crc_out_en = 1; // Enable CRC calculation
|
crc_out = 32'hffffffff; // Initialize outgoing CRC
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
|
calculate_crc(1'b0);
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=2; i>=0; i=i-1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
|
|
calculate_crc(command[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
|
|
if (last_wb_cmd == `CPU_WRITE32)
|
if (last_wb_cmd == `CPU_WRITE32)
|
| Line 1344... |
Line 1291... |
if (len>0) // When CPU_WRITEx was previously activated, data needs to be shifted.
|
if (len>0) // When CPU_WRITEx was previously activated, data needs to be shifted.
|
begin
|
begin
|
for (i=len; i>=0; i=i-1)
|
for (i=len; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 data[i];
|
tdi_pad_i<=#1 data[i];
|
|
calculate_crc(data[i]);
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
end
|
end
|
|
|
crc_out_en = 0; // Disable CRC calculation
|
|
crc_out_shift = 1; // Enable CRC shifting
|
|
|
|
for(i=31; i>=0; i=i-1)
|
for(i=31; i>=0; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
tdi_pad_i<=#1 ~crc_out; // error crc
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
else
|
else
|
tdi_pad_i<=#1 crc_out; // ok crc
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
crc_in = 32'hffffffff; // Initialize incoming CRC
|
|
|
if (last_wb_cmd == `CPU_READ32)
|
if (last_wb_cmd == `CPU_READ32)
|
len = 32;
|
len = 32;
|
else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
|
else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
|
len = 8;
|
len = 8;
|
| Line 1392... |
Line 1335... |
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
if (~crc_match_in)
|
begin
|
begin
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
$stop;
|
$stop;
|
end
|
end
|
| Line 1419... |
Line 1361... |
in_data_le[30:0] <= #1 in_data_le[31:1];
|
in_data_le[30:0] <= #1 in_data_le[31:1];
|
end
|
end
|
|
|
|
|
|
|
|
// Calculating outgoing CRC
|
|
task calculate_crc;
|
|
input data;
|
|
|
|
begin
|
|
crc_out[0] <= #1 data ^ crc_out[31];
|
|
crc_out[1] <= #1 data ^ crc_out[0] ^ crc_out[31];
|
|
crc_out[2] <= #1 data ^ crc_out[1] ^ crc_out[31];
|
|
crc_out[3] <= #1 crc_out[2];
|
|
crc_out[4] <= #1 data ^ crc_out[3] ^ crc_out[31];
|
|
crc_out[5] <= #1 data ^ crc_out[4] ^ crc_out[31];
|
|
crc_out[6] <= #1 crc_out[5];
|
|
crc_out[7] <= #1 data ^ crc_out[6] ^ crc_out[31];
|
|
crc_out[8] <= #1 data ^ crc_out[7] ^ crc_out[31];
|
|
crc_out[9] <= #1 crc_out[8];
|
|
crc_out[10] <= #1 data ^ crc_out[9] ^ crc_out[31];
|
|
crc_out[11] <= #1 data ^ crc_out[10] ^ crc_out[31];
|
|
crc_out[12] <= #1 data ^ crc_out[11] ^ crc_out[31];
|
|
crc_out[13] <= #1 crc_out[12];
|
|
crc_out[14] <= #1 crc_out[13];
|
|
crc_out[15] <= #1 crc_out[14];
|
|
crc_out[16] <= #1 data ^ crc_out[15] ^ crc_out[31];
|
|
crc_out[17] <= #1 crc_out[16];
|
|
crc_out[18] <= #1 crc_out[17];
|
|
crc_out[19] <= #1 crc_out[18];
|
|
crc_out[20] <= #1 crc_out[19];
|
|
crc_out[21] <= #1 crc_out[20];
|
|
crc_out[22] <= #1 data ^ crc_out[21] ^ crc_out[31];
|
|
crc_out[23] <= #1 data ^ crc_out[22] ^ crc_out[31];
|
|
crc_out[24] <= #1 crc_out[23];
|
|
crc_out[25] <= #1 crc_out[24];
|
|
crc_out[26] <= #1 data ^ crc_out[25] ^ crc_out[31];
|
|
crc_out[27] <= #1 crc_out[26];
|
|
crc_out[28] <= #1 crc_out[27];
|
|
crc_out[29] <= #1 crc_out[28];
|
|
crc_out[30] <= #1 crc_out[29];
|
|
crc_out[31] <= #1 crc_out[30];
|
|
end
|
|
endtask // calculate_crc
|
|
|
|
|
|
// Calculating and checking input CRC
|
|
always @(posedge tck_pad_i)
|
|
begin
|
|
crc_in[0] <= #1 tdo ^ crc_in[31];
|
|
crc_in[1] <= #1 tdo ^ crc_in[0] ^ crc_in[31];
|
|
crc_in[2] <= #1 tdo ^ crc_in[1] ^ crc_in[31];
|
|
crc_in[3] <= #1 crc_in[2];
|
|
crc_in[4] <= #1 tdo ^ crc_in[3] ^ crc_in[31];
|
|
crc_in[5] <= #1 tdo ^ crc_in[4] ^ crc_in[31];
|
|
crc_in[6] <= #1 crc_in[5];
|
|
crc_in[7] <= #1 tdo ^ crc_in[6] ^ crc_in[31];
|
|
crc_in[8] <= #1 tdo ^ crc_in[7] ^ crc_in[31];
|
|
crc_in[9] <= #1 crc_in[8];
|
|
crc_in[10] <= #1 tdo ^ crc_in[9] ^ crc_in[31];
|
|
crc_in[11] <= #1 tdo ^ crc_in[10] ^ crc_in[31];
|
|
crc_in[12] <= #1 tdo ^ crc_in[11] ^ crc_in[31];
|
|
crc_in[13] <= #1 crc_in[12];
|
|
crc_in[14] <= #1 crc_in[13];
|
|
crc_in[15] <= #1 crc_in[14];
|
|
crc_in[16] <= #1 tdo ^ crc_in[15] ^ crc_in[31];
|
|
crc_in[17] <= #1 crc_in[16];
|
|
crc_in[18] <= #1 crc_in[17];
|
|
crc_in[19] <= #1 crc_in[18];
|
|
crc_in[20] <= #1 crc_in[19];
|
|
crc_in[21] <= #1 crc_in[20];
|
|
crc_in[22] <= #1 tdo ^ crc_in[21] ^ crc_in[31];
|
|
crc_in[23] <= #1 tdo ^ crc_in[22] ^ crc_in[31];
|
|
crc_in[24] <= #1 crc_in[23];
|
|
crc_in[25] <= #1 crc_in[24];
|
|
crc_in[26] <= #1 tdo ^ crc_in[25] ^ crc_in[31];
|
|
crc_in[27] <= #1 crc_in[26];
|
|
crc_in[28] <= #1 crc_in[27];
|
|
crc_in[29] <= #1 crc_in[28];
|
|
crc_in[30] <= #1 crc_in[29];
|
|
crc_in[31] <= #1 crc_in[30];
|
|
end
|
|
|
|
assign crc_match_in = crc_in == 32'h0;
|
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
| Line 1459... |
Line 1480... |
|
|
|
|
|
|
|
|
// Detecting CRC error
|
// Detecting CRC error
|
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en)
|
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end)
|
begin
|
begin
|
#2;
|
#2;
|
if (~dbg_tb.i_dbg_top.crc_match)
|
if (~dbg_tb.i_dbg_top.crc_match)
|
begin
|
begin
|
$display("\t\tCRC ERROR !!!");
|
$display("\t\tCRC ERROR !!!");
|
