| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2002/03/12 14:32:26 mohor
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// Few outputs for boundary scan chain added.
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//
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// Revision 1.10 2002/03/08 15:27:08 mohor
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// Revision 1.10 2002/03/08 15:27:08 mohor
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// Structure changed. Hooks for jtag chain added.
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// Structure changed. Hooks for jtag chain added.
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//
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//
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// Revision 1.9 2001/10/19 11:39:20 mohor
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// Revision 1.9 2001/10/19 11:39:20 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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| Line 139... |
Line 142... |
wire CHAIN_SELECTSelected;
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wire CHAIN_SELECTSelected;
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wire DEBUGSelected;
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wire DEBUGSelected;
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wire TDOData_dbg;
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wire TDOData_dbg;
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wire BypassRegister;
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wire BypassRegister;
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wire EXTESTSelected;
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wire EXTESTSelected;
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wire [3:0] mon_cntl_o;
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// Connecting TAP module
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// Connecting TAP module
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tap_top i_tap_top
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tap_top i_tap_top
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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.tdo_pad_o(P_TDO), .tdo_padoen_o(tdo_padoen_o),
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.tdo_pad_o(P_TDO), .tdo_padoe_o(tdo_padoe_o),
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// TAP states
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.CaptureDR(CaptureDR),
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.CaptureDR(CaptureDR),
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| Line 184... |
Line 188... |
.DEBUGSelected(DEBUGSelected),
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.DEBUGSelected(DEBUGSelected),
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// TAP signals
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// TAP signals
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.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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.BypassRegister(BypassRegister)
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.BypassRegister(BypassRegister),
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.mon_cntl_o(mon_cntl_o)
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);
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);
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reg TestEnabled;
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reg TestEnabled;
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| Line 291... |
Line 298... |
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
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WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
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WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
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WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
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WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
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WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
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WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
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WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
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WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
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WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
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WriteRegister(32'h0000000d, `MON_CNTL_ADR, 8'h5a); // {data, addr, crc}
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(`MON_CNTL_ADR, 8'ha0); // {addr, crc}
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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//
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//
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