| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.12 2004/01/14 22:59:18 mohor
|
|
// Temp version.
|
|
//
|
// Revision 1.11 2004/01/14 12:29:40 mohor
|
// Revision 1.11 2004/01/14 12:29:40 mohor
|
// temp version. Resets will be changed in next version.
|
// temp version. Resets will be changed in next version.
|
//
|
//
|
// Revision 1.10 2004/01/13 11:28:14 mohor
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// Revision 1.10 2004/01/13 11:28:14 mohor
|
// tmp version.
|
// tmp version.
|
| Line 125... |
Line 128... |
input crc_match_i;
|
input crc_match_i;
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output crc_en_o;
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output crc_en_o;
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output shift_crc_o;
|
output shift_crc_o;
|
input rst_i;
|
input rst_i;
|
// WISHBONE common signals
|
// WISHBONE common signals
|
input wb_clk_i; // WISHBONE clock
|
input wb_clk_i;
|
|
|
// WISHBONE master interface
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// WISHBONE master interface
|
output [31:0] wb_adr_o;
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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| Line 175... |
Line 178... |
|
|
reg [2:0] cmd, cmd_old, dr_cmd_latched;
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reg [2:0] cmd, cmd_old, dr_cmd_latched;
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reg [31:0] adr;
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reg [31:0] adr;
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reg [15:0] len;
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reg [15:0] len;
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reg start_rd_tck;
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reg start_rd_tck;
|
|
reg rd_tck_started;
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reg start_rd_sync1;
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reg start_rd_sync1;
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reg start_wb_rd;
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reg start_wb_rd;
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reg start_wb_rd_q;
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reg start_wb_rd_q;
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reg start_wr_tck;
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reg start_wr_tck;
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reg start_wr_sync1;
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reg start_wr_sync1;
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| Line 206... |
Line 210... |
|
|
reg [`STATUS_LEN -1:0] status;
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reg [`STATUS_LEN -1:0] status;
|
|
|
reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_error, wb_error_sync, wb_error_tck;
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reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
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reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
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|
reg underrun_tck;
|
|
|
reg busy_wb;
|
reg busy_wb;
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reg busy_tck;
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reg busy_tck;
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reg wb_end;
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reg wb_end;
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reg wb_end_rst;
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reg wb_end_rst;
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reg wb_end_rst_sync;
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reg wb_end_rst_sync;
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reg wb_end_sync;
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reg wb_end_sync;
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reg wb_end_tck, wb_end_tck_q;
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reg wb_end_tck, wb_end_tck_q;
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reg busy_sync;
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reg busy_sync;
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reg [799:0] TDO_WISHBONE;
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reg [799:0] tdo_text;
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reg [399:0] latching_data;
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reg [399:0] latching_data_text;
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reg latch_data;
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reg [199:0] status_text;
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|
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
|
reg read_cycle;
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reg read_cycle;
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reg write_cycle;
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reg write_cycle;
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reg [2:0] rw_type;
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reg [2:0] rw_type;
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wire [31:0] input_data;
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wire [31:0] input_data;
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|
|
wire len_eq_0;
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wire len_eq_0;
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wire crc_cnt_31;
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wire crc_cnt_31;
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|
|
|
reg [1:0] ptr;
|
|
reg [2:0] fifo_cnt;
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|
wire fifo_full;
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wire fifo_empty;
|
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reg [7:0] mem [0:3];
|
|
reg [2:0] mem_ptr;
|
|
reg wishbone_ce_sync;
|
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reg wishbone_ce_rst;
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|
wire go_prelim;
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|
|
|
|
|
|
assign enable = wishbone_ce_i & shift_dr_i;
|
assign enable = wishbone_ce_i & shift_dr_i;
|
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
|
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
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assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
|
|
|
reg [1:0] ptr;
|
|
|
|
|
|
|
// Selecting where to take the data from
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
ptr <= #1 2'h0;
|
ptr <= #1 2'h0;
|
else if (read_cycle & crc_cnt_31) // first latch
|
else if (read_cycle & crc_cnt_31) // first latch
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| Line 245... |
Line 263... |
else if (read_cycle & byte & (~byte_q))
|
else if (read_cycle & byte & (~byte_q))
|
ptr <= ptr + 1'd1;
|
ptr <= ptr + 1'd1;
|
end
|
end
|
|
|
|
|
|
// Shift register for shifting in and out the data
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (read_cycle & crc_cnt_31)
|
if (read_cycle & crc_cnt_31)
|
begin
|
begin
|
dr[31:0] <= #1 input_data[31:0];
|
dr[31:0] <= #1 input_data[31:0];
|
latching_data = "First latch";
|
latch_data <= #1 1'b1;
|
|
latching_data_text = "First latch";
|
end
|
end
|
else if (read_cycle & crc_cnt_end)
|
else if (read_cycle & crc_cnt_end)
|
begin
|
begin
|
case (rw_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : begin
|
`WB_READ8 : begin
|
| Line 265... |
Line 284... |
2'b00 : dr[31:24] <= #1 input_data[31:24];
|
2'b00 : dr[31:24] <= #1 input_data[31:24];
|
2'b01 : dr[31:24] <= #1 input_data[23:16];
|
2'b01 : dr[31:24] <= #1 input_data[23:16];
|
2'b10 : dr[31:24] <= #1 input_data[15:8];
|
2'b10 : dr[31:24] <= #1 input_data[15:8];
|
2'b11 : dr[31:24] <= #1 input_data[7:0];
|
2'b11 : dr[31:24] <= #1 input_data[7:0];
|
endcase
|
endcase
|
latching_data = "8 bit latched";
|
latch_data <= #1 1'b1;
|
|
latching_data_text = "8 bit latched";
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:24] <= #1 {dr[30:24], 1'b0};
|
dr[31:24] <= #1 {dr[30:24], 1'b0};
|
latching_data = "8 bit shifted";
|
latch_data <= #1 1'b0;
|
|
latching_data_text = "8 bit shifted";
|
end
|
end
|
end
|
end
|
`WB_READ16: begin
|
`WB_READ16: begin
|
if(half & (~half_q))
|
if(half & (~half_q))
|
begin
|
begin
|
if (ptr[1])
|
if (ptr[1])
|
dr[31:16] <= #1 input_data[31:16];
|
|
else
|
|
dr[31:16] <= #1 input_data[15:0];
|
dr[31:16] <= #1 input_data[15:0];
|
latching_data = "16 bit latched";
|
else
|
|
dr[31:16] <= #1 input_data[31:16];
|
|
latching_data_text = "16 bit latched";
|
|
latch_data <= #1 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dr[31:16] <= #1 {dr[30:16], 1'b0};
|
dr[31:16] <= #1 {dr[30:16], 1'b0};
|
latching_data = "16 bit shifted";
|
latch_data <= #1 1'b0;
|
|
latching_data_text = "16 bit shifted";
|
end
|
end
|
end
|
end
|
`WB_READ32: begin
|
`WB_READ32: begin
|
if(long & (~long_q))
|
if(long & (~long_q))
|
begin
|
begin
|
dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latching_data = "32 bit latched";
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latch_data <= #1 1'b1;
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|
latching_data_text = "32 bit latched";
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end
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end
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else
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else
|
begin
|
begin
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
dr[31:0] <= #1 {dr[30:0], 1'b0};
|
latching_data = "32 bit shifted";
|
latch_data <= #1 1'b0;
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|
latching_data_text = "32 bit shifted";
|
end
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end
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end
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end
|
endcase
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endcase
|
end
|
end
|
else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
|
else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
|
begin
|
begin
|
dr <= #1 {dr[49:0], tdi_i};
|
dr <= #1 {dr[49:0], tdi_i};
|
latching_data = "tdi shifted in";
|
latch_data <= #1 1'b0;
|
|
latching_data_text = "tdi shifted in";
|
end
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end
|
else
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else
|
latching_data = "nothing";
|
latching_data_text = "nothing";
|
end
|
end
|
|
|
|
|
assign cmd_cnt_en = enable & (~cmd_cnt_end);
|
assign cmd_cnt_en = enable & (~cmd_cnt_end);
|
|
|
|
|
|
// Command counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
cmd_cnt <= #1 'h0;
|
cmd_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
| Line 327... |
Line 355... |
end
|
end
|
|
|
|
|
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
|
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
|
|
|
|
|
|
// Address/length counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
addr_len_cnt <= #1 'h0;
|
addr_len_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
| Line 340... |
Line 370... |
end
|
end
|
|
|
|
|
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
|
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
|
|
|
|
|
|
// Data counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
| Line 373... |
Line 405... |
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
|
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
|
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
|
assign dr_go = dr[2:0] == `WB_GO;
|
assign dr_go = dr[2:0] == `WB_GO;
|
|
|
|
|
|
// Latching instruction
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
begin
|
begin
|
dr_cmd_latched = 3'h0;
|
dr_cmd_latched = 3'h0;
|
| Line 392... |
Line 425... |
dr_go_latched <= #1 dr_go;
|
dr_go_latched <= #1 dr_go;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
// Upper limit. Address/length counter counts until this value is reached
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (cmd_cnt == 2'h2)
|
if (cmd_cnt == 2'h2)
|
begin
|
begin
|
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
|
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
|
| Line 404... |
Line 438... |
addr_len_cnt_limit = 6'd48;
|
addr_len_cnt_limit = 6'd48;
|
end
|
end
|
end
|
end
|
|
|
|
|
wire go_prelim;
|
|
|
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
|
|
|
|
|
|
// Upper limit. Data counter counts until this value is reached.
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
data_cnt_limit = {len, 3'b000};
|
data_cnt_limit = {len, 3'b000};
|
end
|
end
|
|
|
|
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
|
|
|
|
|
// crc counter
|
// crc counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 'h0;
|
| Line 443... |
Line 477... |
cmd_cnt_end_q <= #1 cmd_cnt_end;
|
cmd_cnt_end_q <= #1 cmd_cnt_end;
|
data_cnt_end_q <= #1 data_cnt_end;
|
data_cnt_end_q <= #1 data_cnt_end;
|
end
|
end
|
|
|
|
|
|
// Status counter is made of 4 serialy connected registers
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
status_cnt1 <= #1 1'b0;
|
status_cnt1 <= #1 1'b0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
| Line 482... |
Line 516... |
end
|
end
|
|
|
|
|
assign status_cnt_end = status_cnt4;
|
assign status_cnt_end = status_cnt4;
|
|
|
reg [199:0] status_text;
|
|
|
// Status register
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
status <= #1 'h0;
|
status <= #1 'h0;
|
status_text <= #1 "reset";
|
status_text <= #1 "reset";
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
begin
|
begin
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
|
status_text <= #1 "!!!READ";
|
status_text <= #1 "!!!READ";
|
end
|
end
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
|
begin
|
begin
|
status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
|
status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
|
status_text <= #1 "READ";
|
status_text <= #1 "READ";
|
end
|
end
|
else if (shift_dr_i & (~status_cnt_end))
|
else if (shift_dr_i & (~status_cnt_end))
|
begin
|
begin
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
| Line 510... |
Line 545... |
end
|
end
|
// Following status is shifted out:
|
// Following status is shifted out:
|
// 1. bit: 1 if crc is OK, else 0
|
// 1. bit: 1 if crc is OK, else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
|
|
// or underrun occured during read (data couldn't be read fast enough)
|
// 4. bit: 1 if WB error occured, else 0
|
// 4. bit: 1 if WB error occured, else 0
|
|
|
|
|
|
// TDO multiplexer
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or cmd_read or crc_match_i or
|
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or cmd_read or crc_match_i or
|
data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr or cmd_go)
|
data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr or cmd_go)
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
TDO_WISHBONE = "busy_tck";
|
tdo_text = "busy_tck";
|
end
|
end
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
TDO_WISHBONE = "crc_match_i";
|
tdo_text = "crc_match_i";
|
end
|
end
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
begin
|
begin
|
tdo_o = dr[31];
|
tdo_o = dr[31];
|
TDO_WISHBONE = "read data";
|
tdo_text = "read data";
|
end
|
end
|
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
|
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
|
begin
|
begin
|
tdo_o = crc_match_reg;
|
tdo_o = crc_match_reg;
|
TDO_WISHBONE = "crc_match_reg";
|
tdo_text = "crc_match_reg";
|
end
|
end
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
begin
|
begin
|
tdo_o = status[0];
|
tdo_o = status[0];
|
TDO_WISHBONE = "status";
|
tdo_text = "status";
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tdo_o = 1'b0;
|
tdo_o = 1'b0;
|
TDO_WISHBONE = "zero while CRC is shifted in";
|
tdo_text = "zero while CRC is shifted in";
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
| Line 557... |
Line 594... |
if(crc_cnt_end & (~crc_cnt_end_q))
|
if(crc_cnt_end & (~crc_cnt_end_q))
|
crc_match_reg <= #1 crc_match_i;
|
crc_match_reg <= #1 crc_match_i;
|
end
|
end
|
|
|
|
|
|
// Latching instruction
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
cmd <= #1 'h0;
|
cmd <= #1 'h0;
|
| Line 578... |
Line 616... |
cmd_go <= #1 dr_go_latched;
|
cmd_go <= #1 dr_go_latched;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
// Latching address
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
begin
|
begin
|
if (dr_write_latched | dr_read_latched)
|
if (dr_write_latched | dr_read_latched)
|
| Line 593... |
Line 632... |
else
|
else
|
set_addr <= #1 1'b0;
|
set_addr <= #1 1'b0;
|
end
|
end
|
|
|
|
|
|
// Length counter
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
|
len <= #1 dr[15:0];
|
len <= #1 dr[15:0];
|
// else if (wb_end_tck & (~wb_end_tck_q))
|
|
else if (start_rd_tck)
|
else if (start_rd_tck)
|
begin
|
begin
|
case (rw_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : len <= #1 len - 1'd1;
|
`WB_READ8 : len <= #1 len - 1'd1;
|
`WB_READ16: len <= #1 len - 2'd2;
|
`WB_READ16: len <= #1 len - 2'd2;
|
| Line 617... |
Line 656... |
// Start wishbone read cycle
|
// Start wishbone read cycle
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered
|
if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else if (read_cycle & crc_cnt_31 & (~len_eq_0)) // Second read after first data is latched
|
else if ((~start_rd_tck) & read_cycle & (~len_eq_0) & (~fifo_full) & (~rd_tck_started))
|
start_rd_tck <= #1 1'b1;
|
|
else if (read_cycle & (~len_eq_0))
|
|
begin
|
|
case (rw_type) // synthesis parallel_case full_case
|
|
`WB_READ8 : begin
|
|
if(byte & (~byte_q))
|
|
start_rd_tck <= #1 1'b1;
|
|
else
|
|
start_rd_tck <= #1 1'b0;
|
|
end
|
|
`WB_READ16: begin
|
|
if(half & (~half_q))
|
|
start_rd_tck <= #1 1'b1;
|
|
else
|
|
start_rd_tck <= #1 1'b0;
|
|
end
|
|
`WB_READ32: begin
|
|
if(long & (~long_q))
|
|
start_rd_tck <= #1 1'b1;
|
start_rd_tck <= #1 1'b1;
|
else
|
else
|
start_rd_tck <= #1 1'b0;
|
start_rd_tck <= #1 1'b0;
|
end
|
end
|
endcase
|
|
end
|
|
else
|
always @ (posedge tck_i)
|
start_rd_tck <= #1 1'b0;
|
begin
|
|
if (update_dr_i)
|
|
rd_tck_started <= #1 1'b0;
|
|
else if (start_rd_tck)
|
|
rd_tck_started <= #1 1'b1;
|
|
else if (wb_end_tck & (~wb_end_tck_q))
|
|
rd_tck_started <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
| Line 734... |
Line 761... |
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb <= #1 set_addr_sync;
|
set_addr_wb_q <= #1 set_addr_wb;
|
set_addr_wb_q <= #1 set_addr_wb;
|
end
|
end
|
|
|
|
|
|
// wb_cyc_o
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
|
else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
|
| Line 745... |
Line 773... |
else if (wb_ack_i | wb_err_i)
|
else if (wb_ack_i | wb_err_i)
|
wb_cyc_o <= #1 1'b0;
|
wb_cyc_o <= #1 1'b0;
|
end
|
end
|
|
|
|
|
|
// wb_adr_o logic
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
|
wb_adr_o <= #1 adr;
|
wb_adr_o <= #1 adr;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
| Line 768... |
Line 796... |
// adr byte | short | long
|
// adr byte | short | long
|
// 0 1000 1100 1111
|
// 0 1000 1100 1111
|
// 1 0100 err err
|
// 1 0100 err err
|
// 2 0010 0011 err
|
// 2 0010 0011 err
|
// 3 0001 err err
|
// 3 0001 err err
|
|
// wb_sel_o logic
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_sel_o[3:0] <= #1 4'h0;
|
wb_sel_o[3:0] <= #1 4'h0;
|
else
|
else
|
| Line 791... |
Line 819... |
assign wb_stb_o = wb_cyc_o;
|
assign wb_stb_o = wb_cyc_o;
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_cti_o = 3'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
assign wb_bte_o = 2'h0; // always performing single access
|
|
|
|
|
|
// Logic for detecting end of transaction
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_end <= #1 1'b0;
|
wb_end <= #1 1'b0;
|
else if (wb_ack_i | wb_err_i)
|
else if (wb_ack_i | wb_err_i)
|
| Line 852... |
Line 881... |
wb_end_rst_sync <= #1 wb_end_tck;
|
wb_end_rst_sync <= #1 wb_end_tck;
|
wb_end_rst <= #1 wb_end_rst_sync;
|
wb_end_rst <= #1 wb_end_rst_sync;
|
end
|
end
|
|
|
|
|
|
// Detecting WB error
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
else if(wb_err_i)
|
else if(wb_err_i)
|
wb_error <= #1 1'b1;
|
wb_error <= #1 1'b1;
|
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
|
wb_error <= #1 1'b0;
|
wb_error <= #1 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
wb_error_sync <= #1 wb_error;
|
wb_error_sync <= #1 wb_error;
|
wb_error_tck <= #1 wb_error_sync;
|
wb_error_tck <= #1 wb_error_sync;
|
end
|
end
|
|
|
|
|
|
// Detecting overrun when write operation.
|
always @ (posedge wb_clk_i or posedge rst_i)
|
always @ (posedge wb_clk_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
wb_overrun <= #1 1'b0;
|
wb_overrun <= #1 1'b0;
|
else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
|
else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
|
| Line 887... |
Line 918... |
wb_overrun_sync <= #1 wb_overrun;
|
wb_overrun_sync <= #1 wb_overrun;
|
wb_overrun_tck <= #1 wb_overrun_sync;
|
wb_overrun_tck <= #1 wb_overrun_sync;
|
end
|
end
|
|
|
|
|
|
// Detecting underrun when read operation
|
|
always @ (posedge tck_i or posedge rst_i)
|
|
begin
|
|
if (rst_i)
|
|
underrun_tck <= #1 1'b0;
|
|
else if(latch_data & fifo_empty & (~data_cnt_end))
|
|
underrun_tck <= #1 1'b1;
|
|
else if(read_cycle & status_reset_en) // error remains active until STATUS read is performed
|
|
underrun_tck <= #1 1'b0;
|
|
end
|
|
|
|
|
|
|
// wb_error is locked until WB_STATUS is performed
|
// wb_error is locked until WB_STATUS is performed
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
| Line 903... |
Line 943... |
else
|
else
|
status_reset_en <= #1 1'b0;
|
status_reset_en <= #1 1'b0;
|
end
|
end
|
|
|
|
|
reg [7:0] mem [0:3];
|
|
reg [2:0] mem_ptr;
|
|
reg wishbone_ce_sync;
|
|
reg wishbone_ce_rst;
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
wishbone_ce_sync <= #1 wishbone_ce_i;
|
wishbone_ce_sync <= #1 wishbone_ce_i;
|
wishbone_ce_rst <= #1 ~wishbone_ce_sync;
|
wishbone_ce_rst <= #1 ~wishbone_ce_sync;
|
end
|
end
|
|
|
|
|
|
// Logic for latching data that is read from wishbone
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if(wishbone_ce_rst)
|
if(wishbone_ce_rst)
|
mem_ptr <= #1 'h0;
|
mem_ptr <= #1 'h0;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
| Line 929... |
Line 965... |
mem_ptr <= #1 mem_ptr + 2'd2;
|
mem_ptr <= #1 mem_ptr + 2'd2;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
// Logic for latching data that is read from wishbone
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if (wb_ack_i)
|
if (wb_ack_i)
|
begin
|
begin
|
case (wb_sel_o) // synthesis parallel_case full_case
|
case (wb_sel_o) // synthesis parallel_case full_case
|
| Line 960... |
Line 997... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
|
|
|
|
|
|
// Fifo counter and empty/full detection
|
|
always @ (posedge tck_i)
|
|
begin
|
|
if (update_dr_i)
|
|
fifo_cnt <= #1 'h0;
|
|
else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing
|
|
begin
|
|
case (rw_type) // synthesis parallel_case full_case
|
|
`WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
|
|
`WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
|
|
`WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4;
|
|
endcase
|
|
end
|
|
else if (~(wb_end_tck & (~wb_end_tck_q)) & latch_data) // decrementing
|
|
begin
|
|
case (rw_type) // synthesis parallel_case full_case
|
|
`WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1;
|
|
`WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2;
|
|
`WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
assign fifo_full = fifo_cnt == 3'h4;
|
|
assign fifo_empty = fifo_cnt == 3'h0;
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
