URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [cpu_behavioral.v] - Diff between revs 101 and 102

Rev 101	Rev 102
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2004/01/17 17:01:25 mohor`
	`// Almost finished.`
	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`include "timescale.v"	`include "timescale.v"
Line 85...	Line 88...
`input cpu_we_i;`	`input cpu_we_i;`
`output cpu_ack_o;`	`output cpu_ack_o;`
`output cpu_rst_o;`	`output cpu_rst_o;`

`reg cpu_clk_o;`	`reg cpu_clk_o;`
`reg [31:0] tmp_data;`	`reg [31:0] cpu_data_o;`

`initial`	`initial`
`begin`	`begin`
`cpu_clk_o = 1'b0;`	`cpu_clk_o = 1'b0;`
`forever #5 cpu_clk_o = ~cpu_clk_o;`	`forever #5 cpu_clk_o = ~cpu_clk_o;`
Line 103...	Line 106...


`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`	`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`
`begin`	`begin`
`if (cpu_rst_i)`	`if (cpu_rst_i)`
`tmp_data <= #1 32'h11111111;`	`cpu_data_o <= #1 32'h11111111;`
`else if ((cpu_addr_i == 32'h32323232) & cpu_we_i & cpu_ack_o)`	`else if ((cpu_addr_i == 32'h32323232) & cpu_we_i & cpu_ack_o)`
`tmp_data <= #1 32'hdeaddead;`	`cpu_data_o <= #1 cpu_data_i + 1'd1;`
`else if ((cpu_addr_i == 32'h08080808) & cpu_we_i & cpu_ack_o)`	`else if ((cpu_addr_i == 32'h08080808) & cpu_we_i & cpu_ack_o)`
`tmp_data <= #1 32'hbeefbeef;`	`cpu_data_o <= #1 cpu_data_i + 2'd2;`
`end`	`end`