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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 99 and 101

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Line 13... Line 13... 
////  All additional information is avaliable in the README.txt   ////
 
////  All additional information is avaliable in the README.txt   ////
 
////  file.                                                       ////
 
////  file.                                                       ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
//// Copyright (C) 2000 - 2003 Authors                            ////
 
//// Copyright (C) 2000 - 2004 Authors                            ////
 
////                                                              ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.25  2004/01/16 14:51:24  mohor
 
 
 
// cpu registers added.
 
 
 
//
 
// Revision 1.24  2004/01/15 10:47:13  mohor
 
// Revision 1.24  2004/01/15 10:47:13  mohor
 
// Working.
 
// Working.
 
//
 
//
 
// Revision 1.23  2004/01/14 22:59:01  mohor
 
// Revision 1.23  2004/01/14 22:59:01  mohor
 
// Temp version.
 
// Temp version.
Line 131... Line 134... 
 
 
 
 
`include "timescale.v"
 
`include "timescale.v"
 
`include "dbg_defines.v"
 
`include "dbg_defines.v"
 
`include "dbg_wb_defines.v"
 
`include "dbg_wb_defines.v"
 
`include "dbg_cpu_defines.v"
 
`include "dbg_cpu_defines.v"
 
//`include "dbg_tb_defines.v"
 
 
 
 
 
 
 
// Test bench
 
// Test bench
 
module dbg_tb;
 
module dbg_tb;
 
 
 
 
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
 
parameter TCLK = 50;   // Clock half period (Clok period = 100 ns => 10 MHz)
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wire        wb_cab_o;
 
wire        wb_cab_o;
 
wire        wb_err_i;
 
wire        wb_err_i;
 
wire  [2:0] wb_cti_o;
 
wire  [2:0] wb_cti_o;
 
wire  [1:0] wb_bte_o;
 
wire  [1:0] wb_bte_o;
 
 
 
 
 
 
 
// CPU signals
 
 
 
wire        cpu_clk_i;
 
 
 
wire [31:0] cpu_addr_o;
 
 
 
wire [31:0] cpu_data_i;
 
 
 
wire [31:0] cpu_data_o;
 
 
 
wire        cpu_bp_i;
 
 
 
wire        cpu_stall_o;
 
 
 
wire        cpu_stall_all_o;
 
 
 
wire        cpu_stb_o;
 
 
 
wire  [`CPU_NUM -1:0]  cpu_sel_o;
 
 
 
wire        cpu_we_o;
 
 
 
wire        cpu_ack_i;
 
 
 
wire        cpu_rst_o;
 
 
 
 
 
// Text used for easier debugging
 
// Text used for easier debugging
 
reg [199:0] test_text;
 
reg [199:0] test_text;
 
reg   [2:0] last_wb_cmd;
 
reg   [2:0] last_wb_cmd;
 
reg [199:0] last_wb_cmd_text;
 
reg [199:0] last_wb_cmd_text;
 
reg  [31:0] wb_data;
 
reg  [31:0] wb_data;
Line 261... Line 277... 
                    .wb_we_o       (wb_we_o),
 
                    .wb_we_o       (wb_we_o),
 
                    .wb_ack_i      (wb_ack_i),
 
                    .wb_ack_i      (wb_ack_i),
 
                    .wb_cab_o      (wb_cab_o),
 
                    .wb_cab_o      (wb_cab_o),
 
                    .wb_err_i      (wb_err_i),
 
                    .wb_err_i      (wb_err_i),
 
                    .wb_cti_o      (wb_cti_o),
 
                    .wb_cti_o      (wb_cti_o),
 
                    .wb_bte_o      (wb_bte_o)
 
                    .wb_bte_o         (wb_bte_o),
 
 
 
 
 
 
 
                    // CPU signals
 
 
 
                    .cpu_clk_i        (cpu_clk_i),
 
 
 
                    .cpu_addr_o       (cpu_addr_o),
 
 
 
                    .cpu_data_i       (cpu_data_i),
 
 
 
                    .cpu_data_o       (cpu_data_o),
 
 
 
                    .cpu_bp_i         (cpu_bp_i),
 
 
 
                    .cpu_stall_o      (cpu_stall_o),
 
 
 
                    .cpu_stall_all_o  (cpu_stall_all_o),
 
 
 
                    .cpu_stb_o        (cpu_stb_o),
 
 
 
                    .cpu_sel_o        (cpu_sel_o),
 
 
 
                    .cpu_we_o         (cpu_we_o),
 
 
 
                    .cpu_ack_i        (cpu_ack_i),
 
 
 
                    .cpu_rst_o        (cpu_rst_o)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                   );
 
                   );
 
 
 
 
 
 
 
 
 
 
 
 
 
// Connecting CRC module that calculates CRC that is shifted into debug
 
// Connecting CRC module that calculates CRC that is shifted into debug
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                    .WE_I (wb_we_o),
 
                    .WE_I (wb_we_o),
 
                    .CAB_I(1'b0)
 
                    .CAB_I(1'b0)
 
                   );
 
                   );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
cpu_behavioral i_cpu_behavioral
 
 
 
                   (
 
 
 
                    // CPU signals
 
 
 
                    .cpu_rst_i        (wb_rst_i),
 
 
 
                    .cpu_clk_o        (cpu_clk_i),
 
 
 
                    .cpu_addr_i       (cpu_addr_o),
 
 
 
                    .cpu_data_o       (cpu_data_i),
 
 
 
                    .cpu_data_i       (cpu_data_o),
 
 
 
                    .cpu_bp_o         (cpu_bp_i),
 
 
 
                    .cpu_stall_i      (cpu_stall_o),
 
 
 
                    .cpu_stall_all_i  (cpu_stall_all_o),
 
 
 
                    .cpu_stb_i        (cpu_stb_o),
 
 
 
                    .cpu_sel_i        (cpu_sel_o),
 
 
 
                    .cpu_we_i         (cpu_we_o),
 
 
 
                    .cpu_ack_o        (cpu_ack_i),
 
 
 
                    .cpu_rst_o        (cpu_rst_o)
 
 
 
                   );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Initial values
 
// Initial values
 
initial
 
initial
 
begin
 
begin
 
  test_enabled = 1'b0;
 
  test_enabled = 1'b0;
 
  crc_out_en = 1'b0;
 
  crc_out_en = 1'b0;
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  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text}
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, result, "go 2"); // {command, ready, addr, length, gen_crc_err, result, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  chain_select(`CPU_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
  chain_select(`CPU_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  // Select cpu0
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_WRITE_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "select cpu 0"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // Read register
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_WRITE_REG, 32'h00000001, 32'h0, 1'b0, result, "cpu_write_reg"); // {command, addr, data, gen_crc_err, result, text}
 
  debug_cpu(`CPU_READ_REG, `CPU_SEL_ADR, 32'h0, 1'b0, result, "cpu_read_reg"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  debug_cpu(`CPU_GO, 32'h0, 32'hff, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // Stall cpu0
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "stall cpu0"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // write to cpu 32-bit
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // write from cpu 32-bit
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // write to cpu 8-bit
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  // write from cpu 8-bit
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
 
 
  #10000;
 
 
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
/*
 
/*
 
  // Testing read and write to CPU0 registers
 
  // Testing read and write to CPU0 registers
 
  #10000;
 
  #10000;
 
  set_instruction(`CHAIN_SELECT);
 
  set_instruction(`CHAIN_SELECT);

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