OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 101 and 102

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 101 Rev 102
Line 41... Line 41...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.26  2004/01/17 17:01:25  mohor
 
// Almost finished.
 
//
// Revision 1.25  2004/01/16 14:51:24  mohor
// Revision 1.25  2004/01/16 14:51:24  mohor
// cpu registers added.
// cpu registers added.
//
//
// Revision 1.24  2004/01/15 10:47:13  mohor
// Revision 1.24  2004/01/15 10:47:13  mohor
// Working.
// Working.
Line 150... Line 153...
wire  tdo_padoe_o;
wire  tdo_padoe_o;
 
 
wire  shift_dr_o;
wire  shift_dr_o;
wire  pause_dr_o;
wire  pause_dr_o;
wire  update_dr_o;
wire  update_dr_o;
 
wire  capture_dr_o;
 
 
wire  extest_select_o;
wire  extest_select_o;
wire  sample_preload_select_o;
wire  sample_preload_select_o;
wire  mbist_select_o;
wire  mbist_select_o;
wire  debug_select_o;
wire  debug_select_o;
Line 229... Line 233...
 
 
                    // TAP states
                    // TAP states
                    .shift_dr_o       (shift_dr_o),
                    .shift_dr_o       (shift_dr_o),
                    .pause_dr_o       (pause_dr_o),
                    .pause_dr_o       (pause_dr_o),
                    .update_dr_o      (update_dr_o),
                    .update_dr_o      (update_dr_o),
 
                    .capture_dr_o     (capture_dr_o),
 
 
                    // Select signals for boundary scan or mbist
                    // Select signals for boundary scan or mbist
                    .extest_select_o  (extest_select_o),
                    .extest_select_o  (extest_select_o),
                    .sample_preload_select_o(sample_preload_select_o),
                    .sample_preload_select_o(sample_preload_select_o),
                    .mbist_select_o   (mbist_select_o),
                    .mbist_select_o   (mbist_select_o),
Line 519... Line 524...
  debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_WRITE32, 32'h32323232, 32'h0, 1'b0, result, "cpu_write_32"); // {command, addr, data, gen_crc_err, result, text}
 
 
  #10000;
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
  // write from cpu 32-bit
  // read from cpu 32-bit
  #10000;
  #10000;
  debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_READ32, 32'h32323232, 32'h0, 1'b0, result, "cpu_read_32"); // {command, addr, data, gen_crc_err, result, text}
 
 
  #10000;
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
Line 533... Line 538...
  debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_WRITE8, 32'h08080808, 32'h0, 1'b0, result, "cpu_write_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
  #10000;
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
  // write from cpu 8-bit
  // read from cpu 8-bit
  #10000;
  #10000;
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
  #10000;
  #10000;
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.