| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.27 2004/01/17 18:01:31 mohor
|
|
// New version.
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|
//
|
// Revision 1.26 2004/01/17 17:01:25 mohor
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// Revision 1.26 2004/01/17 17:01:25 mohor
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// Almost finished.
|
// Almost finished.
|
//
|
//
|
// Revision 1.25 2004/01/16 14:51:24 mohor
|
// Revision 1.25 2004/01/16 14:51:24 mohor
|
// cpu registers added.
|
// cpu registers added.
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| Line 214... |
Line 217... |
|
|
reg crc_out_en;
|
reg crc_out_en;
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reg crc_out_shift;
|
reg crc_out_shift;
|
wire crc_out;
|
wire crc_out;
|
|
|
|
reg crc_in_en;
|
|
wire crc_match_in;
|
|
|
|
|
|
|
wire tdo;
|
wire tdo;
|
|
|
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
|
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
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| Line 321... |
Line 327... |
);
|
);
|
|
|
|
|
|
|
|
|
|
// Connecting CRC module that calculates CRC that is shifted from debug to bench
|
|
dbg_crc32_d1 crc32_bench_in
|
|
(
|
|
.data (tdo),
|
|
.enable (crc_in_en),
|
|
.shift (1'b0),
|
|
.rst (wb_rst_i),
|
|
.sync_rst (update_dr_o),
|
|
.crc_out (),
|
|
.clk (tck_pad_i),
|
|
.crc_match (crc_match_in)
|
|
);
|
|
|
|
|
|
|
|
|
wb_slave_behavioral wb_slave
|
wb_slave_behavioral wb_slave
|
(
|
(
|
.CLK_I (wb_clk_i),
|
.CLK_I (wb_clk_i),
|
.RST_I (wb_rst_i),
|
.RST_I (wb_rst_i),
|
.ACK_O (wb_ack_i),
|
.ACK_O (wb_ack_i),
|
| Line 367... |
Line 389... |
initial
|
initial
|
begin
|
begin
|
test_enabled = 1'b0;
|
test_enabled = 1'b0;
|
crc_out_en = 1'b0;
|
crc_out_en = 1'b0;
|
crc_out_shift = 1'b0;
|
crc_out_shift = 1'b0;
|
|
crc_in_en = 1'b0;
|
wb_data = 32'h01234567;
|
wb_data = 32'h01234567;
|
trst_pad_i = 1'b1;
|
trst_pad_i = 1'b1;
|
tms_pad_i = 1'hz;
|
tms_pad_i = 1'hz;
|
tck_pad_i = 1'hz;
|
tck_pad_i = 1'hz;
|
tdi_pad_i = 1'hz;
|
tdi_pad_i = 1'hz;
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| Line 545... |
Line 568... |
debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
|
debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
|
|
|
#10000;
|
#10000;
|
debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
/*
|
// Testing read and write to CPU0 registers
|
// Testing read and write to CPU0 registers
|
#10000;
|
#10000;
|
set_instruction(`CHAIN_SELECT);
|
set_instruction(`CHAIN_SELECT);
|
chain_select(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
|
chain_select(`CPU_DEBUG_CHAIN_0, 8'h12); // {chain, crc}
|
| Line 716... |
Line 751... |
|
|
crc_out_shift = 0; // Disable CRC shifting
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
tdi_pad_i<=#1 'hz; // tri-state
|
tdi_pad_i<=#1 'hz; // tri-state
|
|
|
gen_clk(`STATUS_LEN); // Generating 5 clocks to read out status.
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1)
|
for(i=0; i<`CRC_LEN -1; i=i+1)
|
gen_clk(1);
|
gen_clk(1);
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
|
begin
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
|
$stop;
|
|
end
|
|
|
tdi_pad_i<=#1 'hz; // tri-state
|
tdi_pad_i<=#1 'hz; // tri-state
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
| Line 763... |
Line 807... |
debug_wishbone_status(command, gen_crc_err);
|
debug_wishbone_status(command, gen_crc_err);
|
last_wb_cmd = `WB_STATUS; last_wb_cmd_text = "WB_STATUS";
|
last_wb_cmd = `WB_STATUS; last_wb_cmd_text = "WB_STATUS";
|
end
|
end
|
`WB_READ8 :
|
`WB_READ8 :
|
begin
|
begin
|
$display("wb_read8 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text);
|
$display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_READ8; last_wb_cmd_text = "WB_READ8";
|
last_wb_cmd = `WB_READ8; last_wb_cmd_text = "WB_READ8";
|
end
|
end
|
`WB_READ16 :
|
`WB_READ16 :
|
begin
|
begin
|
$display("wb_read16 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text);
|
$display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_READ16; last_wb_cmd_text = "WB_READ16";
|
last_wb_cmd = `WB_READ16; last_wb_cmd_text = "WB_READ16";
|
end
|
end
|
`WB_READ32 :
|
`WB_READ32 :
|
begin
|
begin
|
$display("wb_read32 (ready=%0d, adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", ready, addr, length, gen_crc_err, text);
|
$display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_READ32; last_wb_cmd_text = "WB_READ32";
|
last_wb_cmd = `WB_READ32; last_wb_cmd_text = "WB_READ32";
|
end
|
end
|
`WB_WRITE8 :
|
`WB_WRITE8 :
|
begin
|
begin
|
$display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
$display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_WRITE8; last_wb_cmd_text = "WB_WRITE8";
|
last_wb_cmd = `WB_WRITE8; last_wb_cmd_text = "WB_WRITE8";
|
end
|
end
|
`WB_WRITE16 :
|
`WB_WRITE16 :
|
begin
|
begin
|
$display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
$display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_WRITE16; last_wb_cmd_text = "WB_WRITE16";
|
last_wb_cmd = `WB_WRITE16; last_wb_cmd_text = "WB_WRITE16";
|
end
|
end
|
`WB_WRITE32 :
|
`WB_WRITE32 :
|
begin
|
begin
|
$display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
$display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
debug_wishbone_set_addr(command, ready, addr, length, gen_crc_err);
|
debug_wishbone_set_addr(command, addr, length, gen_crc_err);
|
last_wb_cmd = `WB_WRITE32; last_wb_cmd_text = "WB_WRITE32";
|
last_wb_cmd = `WB_WRITE32; last_wb_cmd_text = "WB_WRITE32";
|
end
|
end
|
`WB_GO :
|
`WB_GO :
|
begin
|
begin
|
$display("wb_go, gen_crc_err=%0d (%0s))", gen_crc_err, text);
|
$display("wb_go, ready=%0d, gen_crc_err=%0d (%0s))", ready, gen_crc_err, text);
|
debug_wishbone_go(command, gen_crc_err);
|
debug_wishbone_go(command, ready, gen_crc_err);
|
// $display("wb_go_tmp, gen_crc_err=0x%0x (%0s))", gen_crc_err, text);
|
// $display("wb_go_tmp, gen_crc_err=0x%0x (%0s))", gen_crc_err, text);
|
// debug_wishbone_go_tmp(command, crc);
|
// debug_wishbone_go_tmp(command, crc);
|
last_wb_cmd = `WB_GO; last_wb_cmd_text = "WB_GO";
|
last_wb_cmd = `WB_GO; last_wb_cmd_text = "WB_GO";
|
end
|
end
|
endcase
|
endcase
|
| Line 816... |
Line 860... |
|
|
|
|
|
|
task debug_wishbone_set_addr;
|
task debug_wishbone_set_addr;
|
input [2:0] command;
|
input [2:0] command;
|
input wait_for_wb_ready; // igor !!! Change this since access only occurs in the "go" stage. Add condition "fifo_empty".
|
|
input [31:0] addr;
|
input [31:0] addr;
|
input [15:0] length;
|
input [15:0] length;
|
input gen_crc_err;
|
input gen_crc_err;
|
integer i;
|
integer i;
|
|
|
| Line 869... |
Line 912... |
end
|
end
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
tdi_pad_i<=#1 'hz;
|
tdi_pad_i<=#1 'hz;
|
if (wait_for_wb_ready)
|
|
begin
|
|
gen_clk(`STATUS_LEN -1); // Generating 4 clocks to read out status. Going to pause_dr at the end
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1); // to exit1_dr
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(1); // to pause_dr
|
|
|
|
while (dbg_tb.tdo_pad_o) // waiting for wb to send "ready"
|
|
begin
|
|
gen_clk(1); // staying in pause_dr
|
|
end
|
|
|
|
tms_pad_i<=#1 1;
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
gen_clk(1); // to exit2_dr
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(1); // to shift_dr
|
|
end
|
|
else
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
|
begin
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
|
$stop;
|
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
end
|
end
|
| Line 949... |
Line 982... |
end
|
end
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
|
begin
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
|
$stop;
|
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
end
|
end
|
| Line 971... |
Line 1014... |
|
|
|
|
|
|
task debug_wishbone_go;
|
task debug_wishbone_go;
|
input [2:0] command;
|
input [2:0] command;
|
|
input wait_for_wb_ready;
|
input gen_crc_err;
|
input gen_crc_err;
|
integer i;
|
integer i;
|
reg [4:0] pointer;
|
reg [4:0] pointer;
|
|
|
begin
|
begin
|
| Line 1014... |
Line 1058... |
end
|
end
|
|
|
crc_out_en = 0; // Disable CRC calculation
|
crc_out_en = 0; // Disable CRC calculation
|
crc_out_shift = 1; // Enable CRC shifting
|
crc_out_shift = 1; // Enable CRC shifting
|
|
|
for(i=31; i>=0; i=i-1)
|
for(i=31; i>=1; i=i-1)
|
begin
|
begin
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
|
tdi_pad_i<=#1 ~crc_out; // error crc
|
|
else
|
|
tdi_pad_i<=#1 crc_out; // ok crc
|
tdi_pad_i<=#1 crc_out; // ok crc
|
|
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
|
if (gen_crc_err) // Generate crc error at last crc bit
|
|
tdi_pad_i<=#1 ~crc_out; // error crc
|
|
else
|
|
tdi_pad_i<=#1 crc_out; // ok crc
|
|
|
|
if (wait_for_wb_ready)
|
|
begin
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
|
crc_out_shift = 0; // Disable CRC shifting
|
crc_out_shift = 0; // Disable CRC shifting
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(1); // to pause_dr
|
|
|
tdi_pad_i<=#1 1'hz;
|
#2; // wait a bit for tdo to activate
|
|
while (tdo) // waiting for wb to send "ready"
|
|
begin
|
|
gen_clk(1); // staying in pause_dr
|
|
end
|
|
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1); // to exit2_dr
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(1); // to shift_dr
|
|
end
|
|
else
|
|
begin
|
|
gen_clk(1); // Last CRC is shifted on this clk
|
|
end
|
|
|
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
|
tdi_pad_i<=#1 1'hz;
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
|
|
if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
begin
|
begin
|
$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
|
$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
|
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
|
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
|
| Line 1048... |
Line 1116... |
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
|
begin
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
|
$stop;
|
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
end
|
end
|
| Line 1179... |
Line 1254... |
end
|
end
|
|
|
crc_out_shift = 0; // Disable CRC shifting
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
tdi_pad_i<=#1 'hz;
|
tdi_pad_i<=#1 'hz;
|
|
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
|
begin
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
|
$stop;
|
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
end
|
end
|
| Line 1265... |
Line 1349... |
|
|
crc_out_shift = 0; // Disable CRC shifting
|
crc_out_shift = 0; // Disable CRC shifting
|
|
|
tdi_pad_i<=#1 1'hz;
|
tdi_pad_i<=#1 1'hz;
|
|
|
|
crc_in_en = 1; // Enable CRC calculation on incoming data
|
|
|
if (last_wb_cmd == `CPU_READ32)
|
if (last_wb_cmd == `CPU_READ32)
|
len = 32;
|
len = 32;
|
else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
|
else if ((last_wb_cmd == `CPU_READ8) | (last_wb_cmd == `CPU_READ_REG))
|
len = 8;
|
len = 8;
|
| Line 1291... |
Line 1376... |
end
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to exit1_dr
|
gen_clk(1); // to exit1_dr
|
|
|
|
crc_in_en = 0; // Disable CRC calculation on incoming data
|
|
if (~crc_match_in)
|
|
begin
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
|
$stop;
|
|
end
|
|
|
tms_pad_i<=#1 1;
|
tms_pad_i<=#1 1;
|
gen_clk(1); // to update_dr
|
gen_clk(1); // to update_dr
|
tms_pad_i<=#1 0;
|
tms_pad_i<=#1 0;
|
gen_clk(1); // to run_test_idle
|
gen_clk(1); // to run_test_idle
|
end
|
end
|
| Line 1391... |
Line 1483... |
begin
|
begin
|
tdi_pad_i<=#1 crc[`CRC_LEN - 1 - i];
|
tdi_pad_i<=#1 crc[`CRC_LEN - 1 - i];
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
gen_clk(`STATUS_LEN); // Generating 5 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1)
|
for(i=0; i<`CRC_LEN -1; i=i+1)
|
begin
|
begin
|
tdi_pad_i<=#1 1'b0;
|
tdi_pad_i<=#1 1'b0;
|
