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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 111 and 113

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Rev 111 Rev 113
Line 41... Line 41... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.29  2004/01/19 13:13:18  mohor
 
 
 
// Define tap_defines.v added to test bench.
 
 
 
//
 
// Revision 1.28  2004/01/19 12:38:10  mohor
 
// Revision 1.28  2004/01/19 12:38:10  mohor
 
// Waiting for "ready" improved.
 
// Waiting for "ready" improved.
 
//
 
//
 
// Revision 1.27  2004/01/17 18:01:31  mohor
 
// Revision 1.27  2004/01/17 18:01:31  mohor
 
// New version.
 
// New version.
Line 216... Line 219... 
wire  mbist_tdi_i;
 
wire  mbist_tdi_i;
 
 
 
 
 
reg   test_enabled;
 
reg   test_enabled;
 
 
 
 
 
reg [31:0] result;
 
reg [31:0] result;
 
 
 
reg [31:0] in_data_le, in_data_be;
 
 
 
reg [31:0] id;
 
reg  crc_out_en;
 
reg  crc_out_en;
 
reg  crc_out_shift;
 
reg  crc_out_shift;
 
wire crc_out;
 
wire crc_out;
 
 
 
 
 
reg  crc_in_en;
 
reg  crc_in_en;
Line 445... Line 449... 
 
 
 
 
  // Testing read and write to internal registers
 
  // Testing read and write to internal registers
 
  #10000;
 
  #10000;
 
 
 
 
 
  set_instruction(`IDCODE);
 
  set_instruction(`IDCODE);
 
  read_id_code;
 
  read_id_code(id);
 
 
 
 
 
 
 
  $display("\tRead ID     = 0x%0x", id);
 
 
 
  $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
 
 
 
 
 
  set_instruction(`DEBUG);
 
  set_instruction(`DEBUG);
 
  #10000;
 
  #10000;
 
 
 
 
 
  chain_select(`WISHBONE_SCAN_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
  chain_select(`WISHBONE_SCAN_CHAIN, 1'b0);   // {chain, gen_crc_err}
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endtask
 
endtask
 
 
 
 
 
 
 
 
 
// Reads the ID code
 
// Reads the ID code
 
task read_id_code;
 
task read_id_code;
 
 
 
  output [31:0] code;
 
 
 
  reg    [31:0] code;
 
  begin
 
  begin
 
    $display("(%0t) Task read_id_code", $time);
 
    $display("(%0t) Task read_id_code", $time);
 
    tms_pad_i<=#1 1;
 
    tms_pad_i<=#1 1;
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 0;
Line 702... Line 711... 
    gen_clk(31);
 
    gen_clk(31);
 
 
 
 
 
    tms_pad_i<=#1 1;        // going out of shiftIR
 
    tms_pad_i<=#1 1;        // going out of shiftIR
 
    gen_clk(1);
 
    gen_clk(1);
 
 
 
 
 
 
 
    code = in_data_le;
 
 
 
 
 
    tdi_pad_i<=#1 'hz; // tri-state
 
    tdi_pad_i<=#1 'hz; // tri-state
 
    gen_clk(1);
 
    gen_clk(1);
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 0;
 
    gen_clk(1);       // we are in RunTestIdle
 
    gen_clk(1);       // we are in RunTestIdle
 
  end
 
  end
Line 1397... Line 1408... 
  end
 
  end
 
endtask       // debug_cpu_go
 
endtask       // debug_cpu_go
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
always @ (posedge tck_pad_i)
 
 
 
begin
 
 
 
  in_data_be[31:1] <= #1 in_data_be[30:0];
 
 
 
  in_data_be[0]    <= #1 tdo;
 
 
 
 
 
 
 
  in_data_le[31]   <= #1 tdo;
 
 
 
  in_data_le[30:0] <= #1 in_data_le[31:1];
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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    endcase
 
    endcase
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
// Print shifted IDCode
 
 
 
reg [31:0] tmp_data;
 
 
 
always @ (posedge tck_pad_i)
 
 
 
begin
 
 
 
  if(dbg_tb.i_tap_top.idcode_select)
 
 
 
    begin
 
 
 
      if(dbg_tb.i_tap_top.shift_dr)
 
 
 
        tmp_data[31:0]<=#1 {dbg_tb.tdo, tmp_data[31:1]};
 
 
 
      else
 
 
 
      if(dbg_tb.i_tap_top.update_dr)
 
 
 
        if (tmp_data[31:0] != `IDCODE_VALUE)
 
 
 
          begin
 
 
 
            $display("(%0t) ERROR: IDCODE not correct", $time);
 
 
 
            $stop;
 
 
 
          end
 
 
 
        else
 
 
 
          $display("\t\tIDCode = 0x%h", tmp_data[31:0]);
 
 
 
    end
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
 
// We never use following states: exit2_ir,  exit2_dr,  pause_ir or pause_dr
 
always @ (posedge tck_pad_i)
 
always @ (posedge tck_pad_i)
 
begin
 
begin
 
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
 
  if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
 
    begin
 
    begin
Line 1463... Line 1456... 
      $stop;
 
      $stop;
 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
// sets the selected scan chain and goes to the RunTestIdle state
 
 
 
task xxx;
 
 
 
  input [3:0]  data;
 
 
 
  input [31:0] crc;
 
 
 
  integer i;
 
 
 
 
 
 
 
  begin
 
 
 
    $display("(%0t) Task xxx", $time);
 
 
 
    tms_pad_i<=#1 1;
 
 
 
    gen_clk(1);
 
 
 
    tms_pad_i<=#1 0;
 
 
 
    gen_clk(2);  // we are in shiftDR
 
 
 
 
 
 
 
    for(i=0; i<4; i=i+1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 data[i];
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    for(i=0; i<`CRC_LEN; i=i+1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 crc[`CRC_LEN - 1 - i];
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
 
 
 
 
 
 
 
 
 
 
 
    for(i=0; i<`CRC_LEN -1; i=i+1)
 
 
 
    begin
 
 
 
      tdi_pad_i<=#1 1'b0;
 
 
 
      gen_clk(1);
 
 
 
    end
 
 
 
 
 
 
 
    tdi_pad_i<=#1 crc[i]; // last crc
 
 
 
    tms_pad_i<=#1 1;
 
 
 
    gen_clk(1);         // to exit1_dr
 
 
 
 
 
 
 
    tdi_pad_i<=#1 'hz;  // tri-state
 
 
 
    tms_pad_i<=#1 1;
 
 
 
    gen_clk(1);         // to update_dr
 
 
 
    tms_pad_i<=#1 0;
 
 
 
    gen_clk(1);         // to run_test_idle
 
 
 
  end
 
 
 
endtask
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Detecting CRC error
 
// Detecting CRC error
 
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en)
 
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en)
 
begin
 
begin

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