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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.34 2004/01/20 14:24:08 mohor
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// Define name changed.
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//
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// Revision 1.33 2004/01/20 14:05:26 mohor
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// Revision 1.33 2004/01/20 14:05:26 mohor
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// Data latching changed when testing WB.
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// Data latching changed when testing WB.
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//
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//
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// Revision 1.32 2004/01/20 10:23:21 mohor
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// Revision 1.32 2004/01/20 10:23:21 mohor
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// More debug data added.
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// More debug data added.
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| Line 372... |
Line 375... |
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// Initial values
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// Initial values
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initial
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initial
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begin
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begin
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test_enabled = 1'b0;
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trst_pad_i = 1'b1;
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trst_pad_i = 1'b1;
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tms_pad_i = 1'hz;
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tms_pad_i = 1'hz;
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tck_pad_i = 1'hz;
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tck_pad_i = 1'hz;
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tdi_pad_i = 1'hz;
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tdi_pad_i = 1'hz;
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#100;
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#100;
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trst_pad_i = 1'b0;
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trst_pad_i = 1'b0;
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#100;
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#100;
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trst_pad_i = 1'b1;
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trst_pad_i = 1'b1;
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#1 test_enabled<=#1 1'b1;
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end
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end
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initial
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initial
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begin
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begin
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test_enabled = 1'b0;
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wb_rst_i = 1'b0;
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wb_rst_i = 1'b0;
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#1000;
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#1000;
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wb_rst_i = 1'b1;
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wb_rst_i = 1'b1;
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#1000;
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#1000;
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wb_rst_i = 1'b0;
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wb_rst_i = 1'b0;
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// Initial values for wishbone slave model
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// Initial values for wishbone slave model
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wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
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wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
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#1 test_enabled<=#1 1'b1;
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end
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end
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initial
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initial
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begin
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begin
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wb_clk_i = 1'b0;
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wb_clk_i = 1'b0;
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| Line 419... |
Line 422... |
reset_tap;
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reset_tap;
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#500;
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#500;
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goto_run_test_idle;
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goto_run_test_idle;
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// Test stall signal
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stall_test;
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// Testing read and write to internal registers
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// Testing read and write to internal registers
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#10000;
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#10000;
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set_instruction(`IDCODE);
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set_instruction(`IDCODE);
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read_id_code(id);
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read_id_code(id);
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Line 576... |
#1000 $stop;
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#1000 $stop;
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end
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end
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task stall_test;
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integer i;
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begin
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$display("\n\n(%0t) stall_test started", $time);
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// Set bp_i active for 1 clock cycle and check is stall is set or not
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check_stall(0); // Should not be set at the beginning
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@ (posedge wb_clk_i);
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#1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b1;
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check_stall(1); // set?
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@ (posedge wb_clk_i);
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#1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b0;
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check_stall(1); // set?
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gen_clk(1);
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check_stall(1); // set?
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// Unstall with register
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set_instruction(`DEBUG);
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chain_select(`CPU_DEBUG_CHAIN, 1'b0); // {chain, gen_crc_err}
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check_stall(1); // set?
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debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
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check_stall(1); // set?
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debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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check_stall(0); // reset?
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// Set stall with register
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debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
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check_stall(0); // reset?
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debug_cpu(`CPU_GO, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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check_stall(1); // set?
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// Unstall with register
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debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
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check_stall(1); // set?
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debug_cpu(`CPU_GO, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
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check_stall(0); // reset?
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$display("\n\n(%0t) stall_test passed\n\n", $time);
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end
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endtask // stall_test
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task check_stall;
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input should_be_set;
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begin
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if (should_be_set && (!cpu_stall_o))
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begin
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$display ("\t\t(%0t) ERROR: cpu_stall_o is not set but should be.", $time);
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$stop;
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end
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if ((!should_be_set) && cpu_stall_o)
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begin
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$display ("\t\t(%0t) ERROR: cpu_stall_o set but shouldn't be.", $time);
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$stop;
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end
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end
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endtask // check_stall
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task initialize_memory;
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task initialize_memory;
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input [31:0] start_addr;
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input [31:0] start_addr;
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input [31:0] length;
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input [31:0] length;
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integer i;
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integer i;
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reg [31:0] addr;
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reg [31:0] addr;
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