URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 121 and 124

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Rev 121	Rev 124
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.36 2004/01/22 13:58:51 mohor`
	`// Port signals are all set to zero after reset.`
	`//`
`// Revision 1.35 2004/01/22 11:07:28 mohor`	`// Revision 1.35 2004/01/22 11:07:28 mohor`
`// test stall_test added.`	`// test stall_test added.`
`//`	`//`
`// Revision 1.34 2004/01/20 14:24:08 mohor`	`// Revision 1.34 2004/01/20 14:24:08 mohor`
`// Define name changed.`	`// Define name changed.`
Line 411...	Line 414...
`forever #5 wb_clk_i = ~wb_clk_i;`	`forever #5 wb_clk_i = ~wb_clk_i;`
`end`	`end`

`always @ (posedge test_enabled)`	`always @ (posedge test_enabled)`
`begin`	`begin`

`$display("//////////////////////////////////////////////////////////////////");`	`$display("//////////////////////////////////////////////////////////////////");`
`$display("// //");`	`$display("// //");`
`$display("// (%0t) dbg_tb starting //", $time);`	`$display("// (%0t) dbg_tb starting //", $time);`
`$display("// //");`	`$display("// //");`
`$display("//////////////////////////////////////////////////////////////////");`	`$display("//////////////////////////////////////////////////////////////////");`

	`$display("TEST: DBG_TEST");`


`initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000`	`initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000`

`reset_tap;`	`reset_tap;`

`#500;`	`#500;`
Line 573...	Line 578...




`#5000 gen_clk(1); // One extra TCLK for debugging purposes`	`#5000 gen_clk(1); // One extra TCLK for debugging purposes`
	`$display("STATUS: passed");`
`$display("\n\nSimulation end.");`	`$display("\n\nSimulation end.");`
`#1000 $stop;`	`#1000 $stop;`

`end`	`end`

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 121 and 124