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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 124 and 128

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Rev 124 Rev 128
Line 41... Line 41... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.37  2004/01/25 14:10:25  mohor
 
 
 
// Display for VATS added.
 
 
 
//
 
// Revision 1.36  2004/01/22 13:58:51  mohor
 
// Revision 1.36  2004/01/22 13:58:51  mohor
 
// Port signals are all set to zero after reset.
 
// Port signals are all set to zero after reset.
 
//
 
//
 
// Revision 1.35  2004/01/22 11:07:28  mohor
 
// Revision 1.35  2004/01/22 11:07:28  mohor
 
// test stall_test added.
 
// test stall_test added.
Line 191... Line 194... 
wire  extest_select_o;
 
wire  extest_select_o;
 
wire  sample_preload_select_o;
 
wire  sample_preload_select_o;
 
wire  mbist_select_o;
 
wire  mbist_select_o;
 
wire  debug_select_o;
 
wire  debug_select_o;
 
 
 
 
 
 
 
reg   rst_i;
 
 
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
// WISHBONE common signals
 
// WISHBONE common signals
 
reg   wb_rst_i;
 
 
 
reg   wb_clk_i;
 
reg   wb_clk_i;
 
 
 
 
 
// WISHBONE master interface
 
// WISHBONE master interface
 
wire [31:0] wb_adr_o;
 
wire [31:0] wb_adr_o;
 
wire [31:0] wb_dat_o;
 
wire [31:0] wb_dat_o;
Line 208... Line 213... 
wire        wb_ack_i;
 
wire        wb_ack_i;
 
wire        wb_cab_o;
 
wire        wb_cab_o;
 
wire        wb_err_i;
 
wire        wb_err_i;
 
wire  [2:0] wb_cti_o;
 
wire  [2:0] wb_cti_o;
 
wire  [1:0] wb_bte_o;
 
wire  [1:0] wb_bte_o;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
// CPU signals
 
// CPU signals
 
wire        cpu_clk_i;
 
wire        cpu_clk_i;
 
wire [31:0] cpu_addr_o;
 
wire [31:0] cpu_addr_o;
 
wire [31:0] cpu_data_i;
 
wire [31:0] cpu_data_i;
 
wire [31:0] cpu_data_o;
 
wire [31:0] cpu_data_o;
Line 222... Line 229... 
wire        cpu_stb_o;
 
wire        cpu_stb_o;
 
wire  [`CPU_NUM -1:0]  cpu_sel_o;
 
wire  [`CPU_NUM -1:0]  cpu_sel_o;
 
wire        cpu_we_o;
 
wire        cpu_we_o;
 
wire        cpu_ack_i;
 
wire        cpu_ack_i;
 
wire        cpu_rst_o;
 
wire        cpu_rst_o;
 
 
 
`endif
 
 
 
 
 
// Text used for easier debugging
 
// Text used for easier debugging
 
reg [199:0] test_text;
 
reg [199:0] test_text;
 
reg   [2:0] last_wb_cmd;
 
reg   [2:0] last_wb_cmd;
 
reg [199:0] last_wb_cmd_text;
 
reg [199:0] last_wb_cmd_text;
Line 290... Line 298... 
// Connecting debug top module
 
// Connecting debug top module
 
dbg_top i_dbg_top  (
 
dbg_top i_dbg_top  (
 
                    .tck_i            (tck_pad_i),
 
                    .tck_i            (tck_pad_i),
 
                    .tdi_i            (tdo_o),
 
                    .tdi_i            (tdo_o),
 
                    .tdo_o            (debug_tdi_i),
 
                    .tdo_o            (debug_tdi_i),
 
 
 
                    .rst_i            (rst_i),
 
 
 
 
 
                    // TAP states
 
                    // TAP states
 
                    .shift_dr_i       (shift_dr_o),
 
                    .shift_dr_i       (shift_dr_o),
 
                    .pause_dr_i       (pause_dr_o),
 
                    .pause_dr_i       (pause_dr_o),
 
                    .update_dr_i      (update_dr_o),
 
                    .update_dr_i      (update_dr_o),
 
 
 
 
 
                    // Instructions
 
                    // Instructions
 
                    .debug_select_i   (debug_select_o),
 
                    .debug_select_i   (debug_select_o)
 
 
 
 
 
 
 
                    `ifdef WISHBONE_SUPPORTED
 
                    // WISHBONE common signals
 
                    // WISHBONE common signals
 
                    .wb_rst_i         (wb_rst_i),
 
                    ,
 
                    .wb_clk_i         (wb_clk_i),
 
                    .wb_clk_i         (wb_clk_i),
 
 
 
 
 
                    // WISHBONE master interface
 
                    // WISHBONE master interface
 
                    .wb_adr_o         (wb_adr_o),
 
                    .wb_adr_o         (wb_adr_o),
 
                    .wb_dat_o         (wb_dat_o),
 
                    .wb_dat_o         (wb_dat_o),
Line 315... Line 325... 
                    .wb_we_o          (wb_we_o),
 
                    .wb_we_o          (wb_we_o),
 
                    .wb_ack_i         (wb_ack_i),
 
                    .wb_ack_i         (wb_ack_i),
 
                    .wb_cab_o         (wb_cab_o),
 
                    .wb_cab_o         (wb_cab_o),
 
                    .wb_err_i         (wb_err_i),
 
                    .wb_err_i         (wb_err_i),
 
                    .wb_cti_o         (wb_cti_o),
 
                    .wb_cti_o         (wb_cti_o),
 
                    .wb_bte_o         (wb_bte_o),
 
                    .wb_bte_o         (wb_bte_o)
 
 
 
                    `endif
 
 
 
 
 
 
 
                    `ifdef CPU_SUPPORTED
 
                    // CPU signals
 
                    // CPU signals
 
 
 
                    ,
 
                    .cpu_clk_i        (cpu_clk_i),
 
                    .cpu_clk_i        (cpu_clk_i),
 
                    .cpu_addr_o       (cpu_addr_o),
 
                    .cpu_addr_o       (cpu_addr_o),
 
                    .cpu_data_i       (cpu_data_i),
 
                    .cpu_data_i       (cpu_data_i),
 
                    .cpu_data_o       (cpu_data_o),
 
                    .cpu_data_o       (cpu_data_o),
 
                    .cpu_bp_i         (cpu_bp_i),
 
                    .cpu_bp_i         (cpu_bp_i),
Line 330... Line 343... 
                    .cpu_stb_o        (cpu_stb_o),
 
                    .cpu_stb_o        (cpu_stb_o),
 
                    .cpu_sel_o        (cpu_sel_o),
 
                    .cpu_sel_o        (cpu_sel_o),
 
                    .cpu_we_o         (cpu_we_o),
 
                    .cpu_we_o         (cpu_we_o),
 
                    .cpu_ack_i        (cpu_ack_i),
 
                    .cpu_ack_i        (cpu_ack_i),
 
                    .cpu_rst_o        (cpu_rst_o)
 
                    .cpu_rst_o        (cpu_rst_o)
 
 
 
                    `endif
 
 
 
 
 
 
 
 
 
 
 
 
 
                   );
 
                   );
 
 
 
 
 
 
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
wb_slave_behavioral wb_slave
 
wb_slave_behavioral wb_slave
 
                   (
 
                   (
 
                    .CLK_I            (wb_clk_i),
 
                    .CLK_I            (wb_clk_i),
 
                    .RST_I            (wb_rst_i),
 
                    .RST_I            (rst_i),
 
                    .ACK_O            (wb_ack_i),
 
                    .ACK_O            (wb_ack_i),
 
                    .ADR_I            (wb_adr_o),
 
                    .ADR_I            (wb_adr_o),
 
                    .CYC_I            (wb_cyc_o),
 
                    .CYC_I            (wb_cyc_o),
 
                    .DAT_O            (wb_dat_i),
 
                    .DAT_O            (wb_dat_i),
 
                    .DAT_I            (wb_dat_o),
 
                    .DAT_I            (wb_dat_o),
Line 354... Line 367... 
                    .SEL_I            (wb_sel_o),
 
                    .SEL_I            (wb_sel_o),
 
                    .STB_I            (wb_stb_o),
 
                    .STB_I            (wb_stb_o),
 
                    .WE_I             (wb_we_o),
 
                    .WE_I             (wb_we_o),
 
                    .CAB_I            (1'b0)
 
                    .CAB_I            (1'b0)
 
                   );
 
                   );
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
cpu_behavioral i_cpu_behavioral
 
cpu_behavioral i_cpu_behavioral
 
                   (
 
                   (
 
                    // CPU signals
 
                    // CPU signals
 
                    .cpu_rst_i        (wb_rst_i),
 
                    .cpu_rst_i        (rst_i),
 
                    .cpu_clk_o        (cpu_clk_i),
 
                    .cpu_clk_o        (cpu_clk_i),
 
                    .cpu_addr_i       (cpu_addr_o),
 
                    .cpu_addr_i       (cpu_addr_o),
 
                    .cpu_data_o       (cpu_data_i),
 
                    .cpu_data_o       (cpu_data_i),
 
                    .cpu_data_i       (cpu_data_o),
 
                    .cpu_data_i       (cpu_data_o),
 
                    .cpu_bp_o         (cpu_bp_i),
 
                    .cpu_bp_o         (cpu_bp_i),
Line 374... Line 388... 
                    .cpu_sel_i        (cpu_sel_o),
 
                    .cpu_sel_i        (cpu_sel_o),
 
                    .cpu_we_i         (cpu_we_o),
 
                    .cpu_we_i         (cpu_we_o),
 
                    .cpu_ack_o        (cpu_ack_i),
 
                    .cpu_ack_o        (cpu_ack_i),
 
                    .cpu_rst_o        (cpu_rst_o)
 
                    .cpu_rst_o        (cpu_rst_o)
 
                   );
 
                   );
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
 
 
// Initial values
 
// Initial values
 
initial
 
initial
Line 395... Line 409... 
end
 
end
 
 
 
 
 
initial
 
initial
 
begin
 
begin
 
  test_enabled = 1'b0;
 
  test_enabled = 1'b0;
 
  wb_rst_i = 1'b0;
 
  rst_i = 1'b0;
 
  #1000;
 
  #1000;
 
  wb_rst_i = 1'b1;
 
  rst_i = 1'b1;
 
  #1000;
 
  #1000;
 
  wb_rst_i = 1'b0;
 
  rst_i = 1'b0;
 
 
 
 
 
  // Initial values for wishbone slave model
 
  // Initial values for wishbone slave model
 
 
 
  `ifdef WISHBONE_SUPPORTED
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
 
 
  `endif
 
  #1 test_enabled<=#1 1'b1;
 
  #1 test_enabled<=#1 1'b1;
 
end
 
end
 
 
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
initial
 
initial
 
begin
 
begin
 
  wb_clk_i = 1'b0;
 
  wb_clk_i = 1'b0;
 
  forever #5 wb_clk_i = ~wb_clk_i;
 
  forever #5 wb_clk_i = ~wb_clk_i;
 
end
 
end
 
 
 
`endif
 
 
 
 
 
always @ (posedge test_enabled)
 
always @ (posedge test_enabled)
 
begin
 
begin
 
  $display("//////////////////////////////////////////////////////////////////");
 
  $display("//////////////////////////////////////////////////////////////////");
 
  $display("//                                                              //");
 
  $display("//                                                              //");
Line 430... Line 448... 
  reset_tap;
 
  reset_tap;
 
 
 
 
 
  #500;
 
  #500;
 
  goto_run_test_idle;
 
  goto_run_test_idle;
 
 
 
 
 
 
 
  `ifdef CPU_SUPPORTED
 
  // Test stall signal
 
  // Test stall signal
 
  stall_test;
 
  stall_test;
 
 
 
  `endif
 
 
 
 
 
  // Testing read and write to internal registers
 
  // Testing read and write to internal registers
 
  #10000;
 
  #10000;
 
 
 
 
 
  set_instruction(`IDCODE);
 
  set_instruction(`IDCODE);
Line 445... Line 465... 
  $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
 
  $display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
 
 
 
 
 
  set_instruction(`DEBUG);
 
  set_instruction(`DEBUG);
 
  #10000;
 
  #10000;
 
 
 
 
 
 
 
  `ifdef WISHBONE_SUPPORTED
 
  chain_select(`WISHBONE_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
  chain_select(`WISHBONE_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
 
 
 
 
//  #10000;
 
 
 
//  xxx(4'b1001, 32'he579b242);
 
 
 
 
 
 
 
  #10000;
 
  #10000;
 
 
 
 
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
Line 464... Line 482... 
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
 
//
 
//
 
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
//  xxx(4'b1001, 32'he579b242);
 
 
 
 
 
 
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
 
  wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2);   // (`ACK_RESPONSE, wbs_waits, wbs_retries);
Line 512... Line 529... 
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}  
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}  
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
 
//  debug_wishbone(`WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
 
  debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
 
 
 
  `endif  // WISHBONE_SUPPORTED
 
 
 
 
 
 
 
  `ifdef CPU_SUPPORTED
 
  #10000;
 
  #10000;
 
  chain_select(`CPU_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
  chain_select(`CPU_DEBUG_CHAIN, 1'b0);   // {chain, gen_crc_err}
 
 
 
 
 
 
 
 
 
 
 
 
Line 567... Line 586... 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
 
  debug_cpu(`CPU_READ8, 32'h08080808, 32'h0, 1'b0, result, "cpu_read_8"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
 
 
  #10000;
 
  #10000;
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
  debug_cpu(`CPU_GO, 32'h0, 32'hdeadbeef, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
 
 
 
  `endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Line 585... Line 604... 
  #1000 $stop;
 
  #1000 $stop;
 
 
 
 
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
task stall_test;
 
task stall_test;
 
  integer i;
 
  integer i;
 
 
 
 
 
  begin
 
  begin
 
    test_text = "stall_test";
 
    test_text = "stall_test";
 
    $display("\n\n(%0t) stall_test started", $time);
 
    $display("\n\n(%0t) stall_test started", $time);
 
 
 
 
 
    // Set bp_i active for 1 clock cycle and check is stall is set or not
 
    // Set bp_i active for 1 clock cycle and check is stall is set or not
 
    check_stall(0); // Should not be set at the beginning
 
    check_stall(0); // Should not be set at the beginning
 
    @ (posedge wb_clk_i);
 
    @ (posedge cpu_clk_i);
 
    #1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b1;
 
    #1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b1;
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
    @ (posedge wb_clk_i);
 
    @ (posedge cpu_clk_i);
 
    #1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b0;
 
    #1 dbg_tb.i_cpu_behavioral.cpu_bp_o = 1'b0;
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
 
 
 
 
 
    gen_clk(1);
 
    gen_clk(1);
 
    #1 check_stall(1); // set?
 
    #1 check_stall(1); // set?
Line 645... Line 665... 
        $display ("\t\t(%0t) ERROR: cpu_stall_o set but shouldn't be.", $time);
 
        $display ("\t\t(%0t) ERROR: cpu_stall_o set but shouldn't be.", $time);
 
        $stop;
 
        $stop;
 
      end
 
      end
 
  end
 
  end
 
endtask   // check_stall
 
endtask   // check_stall
 
 
 
`endif
 
 
 
 
 
 
 
 
 
task initialize_memory;
 
task initialize_memory;
 
  input [31:0] start_addr;
 
  input [31:0] start_addr;
 
  input [31:0] length;
 
  input [31:0] length;
Line 656... Line 677... 
  reg [31:0] addr;
 
  reg [31:0] addr;
 
  begin
 
  begin
 
    for (i=0; i<length; i=i+4)  // This data will be return from wb slave
 
    for (i=0; i<length; i=i+4)  // This data will be return from wb slave
 
      begin
 
      begin
 
        addr = start_addr + i;
 
        addr = start_addr + i;
 
 
 
        `ifdef WISHBONE_SUPPORTED
 
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
 
        wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf);    // adr, data, sel
 
 
 
        `endif
 
      end
 
      end
 
    for (i=0; i<4096; i=i+1)  // This data will be written to wb slave
 
    for (i=0; i<4096; i=i+1)  // This data will be written to wb slave
 
      begin
 
      begin
 
        wb_data[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
 
        wb_data[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
 
      end
 
      end
Line 840... Line 863... 
endtask   // chain_select
 
endtask   // chain_select
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`ifdef WISHBONE_SUPPORTED
 
task debug_wishbone;
 
task debug_wishbone;
 
  input [2:0]   command;
 
  input [2:0]   command;
 
  input         ready;
 
  input         ready;
 
  input [31:0]  addr;
 
  input [31:0]  addr;
 
  input [15:0]  length;
 
  input [15:0]  length;
Line 1190... Line 1214... 
    gen_clk(1);         // to run_test_idle
 
    gen_clk(1);         // to run_test_idle
 
  end
 
  end
 
endtask       // debug_wishbone_go
 
endtask       // debug_wishbone_go
 
 
 
 
 
 
 
 
 
 
 
`endif // WISHBONE_SUPPORTED
 
 
 
 
 
 
 
 
 
 
 
`ifdef CPU_SUPPORTED
 
task debug_cpu;
 
task debug_cpu;
 
  input [2:0]   command;
 
  input [2:0]   command;
 
  input [31:0]  addr;
 
  input [31:0]  addr;
 
  input [31:0]  data;
 
  input [31:0]  data;
 
  input         gen_crc_err;
 
  input         gen_crc_err;
Line 1441... Line 1467... 
    gen_clk(1);         // to update_dr
 
    gen_clk(1);         // to update_dr
 
    tms_pad_i<=#1 0;
 
    tms_pad_i<=#1 0;
 
    gen_clk(1);         // to run_test_idle
 
    gen_clk(1);         // to run_test_idle
 
  end
 
  end
 
endtask       // debug_cpu_go
 
endtask       // debug_cpu_go
 
 
 
`endif  // CPU_SUPPORTED
 
 
 
 
 
 
 
 
 
 
 
 
 
always @ (posedge tck_pad_i)
 
always @ (posedge tck_pad_i)
 
begin
 
begin
Line 1574... Line 1601... 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Detecting CRC error
 
// Detecting CRC error
 
always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end or posedge dbg_tb.i_dbg_top.chain_latch_en or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end)
 
always @ (
 
 
 
           posedge dbg_tb.i_dbg_top.chain_latch_en
 
 
 
           `ifdef WISHBONE_SUPPORTED
 
 
 
           or posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end
 
 
 
           `endif
 
 
 
           `ifdef CPU_SUPPORTED
 
 
 
           or posedge dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt_end
 
 
 
           `endif
 
 
 
         )
 
 
 
 
 
 
 
 
 
begin
 
begin
 
  #2;
 
  #2;
 
  if (~dbg_tb.i_dbg_top.crc_match)
 
  if (~dbg_tb.i_dbg_top.crc_match)
 
    begin
 
    begin
 
      $display("\t\tCRC ERROR !!!");
 
      $display("\t\tCRC ERROR !!!");
Line 1586... Line 1623... 
    end
 
    end
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
// Detecting errors in counters
 
 
 
always @ (dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_en or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en or
 
 
 
          dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
 
 
 
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt2 or
 
 
 
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt3 or
 
 
 
          //dbg_tb.i_dbg_top.i_dbg_wb.status_cnt4
 
 
 
          // dbg_tb.i_dbg_top.i_dbg_wb. or
 
 
 
         )
 
 
 
begin
 
 
 
  if ((~dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end) & (
 
 
 
                                                  dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en |
 
 
 
                                                  dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en     |
 
 
 
                                                  dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en      |
 
 
 
                                                  dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
 
 
 
                                                 )
 
 
 
     )
 
 
 
    begin
 
 
 
      $display("\n\n\t\t(%0t) ERROR in counters !!!", $time);
 
 
 
      #10000;
 
 
 
      $stop;
 
 
 
    end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule // dbg_tb
 
endmodule // dbg_tb
 
 
 
 
 
 
 
 
 
 
 
 
 
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