| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/03/08 15:27:08 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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// Revision 1.9 2001/10/19 11:39:20 mohor
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// Revision 1.9 2001/10/19 11:39:20 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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// few different cores in a single project.
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//
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//
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// Revision 1.8 2001/10/17 10:39:17 mohor
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// Revision 1.8 2001/10/17 10:39:17 mohor
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| Line 125... |
Line 128... |
wire wb_we_i;
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wire wb_we_i;
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reg wb_ack_o;
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reg wb_ack_o;
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wire wb_cab_i;
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wire wb_cab_i;
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reg wb_err_o;
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reg wb_err_o;
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wire ShiftDR;
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wire Exit1DR;
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wire UpdateDR;
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wire UpdateDR_q;
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wire CaptureDR;
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wire IDCODESelected;
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wire CHAIN_SELECTSelected;
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wire DEBUGSelected;
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wire TDOData_dbg;
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wire BypassRegister;
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wire EXTESTSelected;
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// Connecting TAP module
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// Connecting TAP module
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tap_top i_tap_top
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tap_top i_tap_top
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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.tdo_pad_o(P_TDO), .tdo_padoen_o(tdo_padoen_o),
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.tdo_pad_o(P_TDO), .tdo_padoen_o(tdo_padoen_o),
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|
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.wb_rst_i(wb_rst_i), .risc_clk_i(Mclk),
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// TAP states
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.risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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.wp_i(Wp), .bp_i(Bp),
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.CaptureDR(CaptureDR),
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.opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
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.risc_stall_o(), .reset_o(),
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// Instructions
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.wb_clk_i(Mclk), .wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
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.DEBUGSelected(DEBUGSelected), .EXTESTSelected(EXTESTSelected),
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.wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i), .wb_we_o(wb_we_i),
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.wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i), .wb_err_i(wb_err_o)
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// TDO from dbg module
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.TDOData_dbg(TDOData_dbg), .BypassRegister(BypassRegister),
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// Boundary Scan Chain
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.bs_chain_i(BS_CHAIN_I)
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|
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);
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);
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dbg_top i_dbg_top
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(
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.risc_clk_i(Mclk), .risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC),
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.risc_data_o(DATAIN_RISC), .wp_i(Wp), .bp_i(Bp), .opselect_o(OpSelect),
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.lsstatus_i(LsStatus), .istatus_i(IStatus), .risc_stall_o(), .reset_o(),
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.wb_rst_i(wb_rst_i), .wb_clk_i(Mclk),
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.wb_adr_o(wb_adr_i), .wb_dat_o(wb_dat_i), .wb_dat_i(wb_dat_o),
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.wb_cyc_o(wb_cyc_i), .wb_stb_o(wb_stb_i), .wb_sel_o(wb_sel_i),
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.wb_we_o(wb_we_i), .wb_ack_i(wb_ack_o), .wb_cab_o(wb_cab_i),
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.wb_err_i(wb_err_o),
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// TAP states
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.ShiftDR(ShiftDR), .Exit1DR(Exit1DR), .UpdateDR(UpdateDR), .UpdateDR_q(UpdateDR_q),
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// Instructions
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.IDCODESelected(IDCODESelected), .CHAIN_SELECTSelected(CHAIN_SELECTSelected),
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.DEBUGSelected(DEBUGSelected),
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// TAP signals
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.trst_in(P_TRST), .tck(P_TCK), .tdi(P_TDI), .TDOData(TDOData_dbg),
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.BypassRegister(BypassRegister)
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);
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reg TestEnabled;
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reg TestEnabled;
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| Line 154... |
Line 198... |
begin
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begin
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TestEnabled<=#Tp 0;
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TestEnabled<=#Tp 0;
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P_TMS<=#Tp 'hz;
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P_TMS<=#Tp 'hz;
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P_TCK<=#Tp 'hz;
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P_TCK<=#Tp 'hz;
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P_TDI<=#Tp 'hz;
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P_TDI<=#Tp 'hz;
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BS_CHAIN_I = 0;
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Wp<=#Tp 0;
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Wp<=#Tp 0;
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Bp<=#Tp 0;
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Bp<=#Tp 0;
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LsStatus<=#Tp 0;
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LsStatus<=#Tp 0;
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IStatus<=#Tp 0;
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IStatus<=#Tp 0;
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| Line 288... |
Line 333... |
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
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#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
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#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
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#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
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#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
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#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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wait(dbg_tb.i_tap_top.TraceEnable)
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wait(dbg_tb.i_dbg_top.TraceEnable)
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@ (posedge Mclk);
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@ (posedge Mclk);
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#1 Bp = 1; // Set breakpoint
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#1 Bp = 1; // Set breakpoint
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repeat(8) @(posedge Mclk);
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repeat(8) @(posedge Mclk);
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wait(dbg_tb.i_tap_top.dbgTrace1.RiscStall)
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wait(dbg_tb.i_dbg_top.dbgTrace1.RiscStall)
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#1 Bp = 0; // Clear breakpoint
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#1 Bp = 0; // Clear breakpoint
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// End: Anything starts trigger, breakpoint starts qualifier */
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// End: Anything starts trigger, breakpoint starts qualifier */
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|
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/* Anything starts qualifier, breakpoint starts trigger
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/* Anything starts qualifier, breakpoint starts trigger
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| Line 304... |
Line 349... |
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
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#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
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#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
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#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
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#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
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#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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wait(dbg_tb.i_tap_top.TraceEnable)
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wait(dbg_tb.i_dbg_top.TraceEnable)
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@ (posedge Mclk)
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@ (posedge Mclk)
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Wp[4] = 1; // Set watchpoint[4]
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Wp[4] = 1; // Set watchpoint[4]
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LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
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LsStatus = 4'h5; // LsStatus[0] and LsStatus[2] are active
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@ (posedge Mclk)
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@ (posedge Mclk)
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Wp[4] = 0; // Clear watchpoint[4]
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Wp[4] = 0; // Clear watchpoint[4]
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| Line 731... |
Line 776... |
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// Print samples that are recorded to the trace buffer
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// Print samples that are recorded to the trace buffer
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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always @ (posedge Mclk)
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always @ (posedge Mclk)
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begin
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begin
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if(dbg_tb.i_tap_top.dbgTrace1.WriteSample)
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if(dbg_tb.i_dbg_top.dbgTrace1.WriteSample)
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$write("\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.i_tap_top.dbgTrace1.WritePointer, {dbg_tb.i_tap_top.dbgTrace1.DataIn, 1'b0, dbg_tb.i_tap_top.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
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$write("\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.i_dbg_top.dbgTrace1.WritePointer, {dbg_tb.i_dbg_top.dbgTrace1.DataIn, 1'b0, dbg_tb.i_dbg_top.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
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end
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end
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`endif
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`endif
|
|
|
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// Print selected instruction
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// Print selected instruction
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| Line 747... |
Line 792... |
end
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end
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always @ (posedge P_TCK)
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always @ (posedge P_TCK)
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begin
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begin
|
if(UpdateIR_q)
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if(UpdateIR_q)
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case(dbg_tb.i_tap_top.JTAG_IR[`IR_LENGTH-1:0])
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case(dbg_tb.i_tap_top.LatchedJTAG_IR[`IR_LENGTH-1:0])
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`EXTEST : $write("\n\tInstruction EXTEST");
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`EXTEST : $write("\n\tInstruction EXTEST");
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`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
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`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
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`IDCODE : $write("\n\tInstruction IDCODE");
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`IDCODE : $write("\n\tInstruction IDCODE");
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`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
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`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
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`INTEST : $write("\n\tInstruction INTEST");
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`INTEST : $write("\n\tInstruction INTEST");
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| Line 768... |
Line 813... |
|
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// Print selected chain
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// Print selected chain
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always @ (posedge P_TCK)
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always @ (posedge P_TCK)
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begin
|
begin
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
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if(dbg_tb.i_tap_top.CHAIN_SELECTSelected & dbg_tb.i_tap_top.UpdateDR_q)
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case(dbg_tb.i_tap_top.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
|
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
|
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
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`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
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`RISC_DEBUG_CHAIN : $write("\nChain RISC_DEBUG_CHAIN");
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`RISC_DEBUG_CHAIN : $write("\nChain RISC_DEBUG_CHAIN");
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`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
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`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
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`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
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`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
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`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
|
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
|
| Line 782... |
Line 827... |
|
|
|
|
// print RISC registers read/write
|
// print RISC registers read/write
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.i_dbg_top.RISCAccess & ~dbg_tb.i_tap_top.i_dbg_top.RISCAccess_q & dbg_tb.i_tap_top.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.RISCAccess & ~dbg_tb.i_dbg_top.RISCAccess_q & dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_tap_top.i_dbg_top.ADDR[31:0], dbg_tb.i_tap_top.i_dbg_top.DataOut[31:0]);
|
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
else
|
else
|
if(dbg_tb.i_tap_top.i_dbg_top.RISCAccess_q & ~dbg_tb.i_tap_top.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_tap_top.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.RISCAccess_q & ~dbg_tb.i_dbg_top.RISCAccess_q2 & ~dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_tap_top.i_dbg_top.ADDR[31:0], dbg_tb.i_tap_top.i_dbg_top.risc_data_i[31:0]);
|
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.risc_data_i[31:0]);
|
end
|
end
|
|
|
|
|
// print registers read/write
|
// print registers read/write
|
always @ (posedge Mclk)
|
always @ (posedge Mclk)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.i_dbg_top.RegAccess_q & ~dbg_tb.i_tap_top.i_dbg_top.RegAccess_q2)
|
if(dbg_tb.i_dbg_top.RegAccess_q & ~dbg_tb.i_dbg_top.RegAccess_q2)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.i_dbg_top.RW)
|
if(dbg_tb.i_dbg_top.RW)
|
$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_tap_top.i_dbg_top.ADDR[4:0], dbg_tb.i_tap_top.i_dbg_top.DataOut[31:0]);
|
$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.DataOut[31:0]);
|
else
|
else
|
$write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_tap_top.i_dbg_top.ADDR[4:0], dbg_tb.i_tap_top.i_dbg_top.RegDataIn[31:0]);
|
$write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.RegDataIn[31:0]);
|
end
|
end
|
end
|
end
|
|
|
|
|
// print CRC error
|
// print CRC error
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
wire CRCErrorReport = ~(dbg_tb.i_tap_top.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.TraceTestScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.CHAIN_SELECTSelected | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RegisterScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.RiscDebugScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.DEBUGSelected & dbg_tb.i_dbg_top.WishboneScanChain));
|
`else // TRACE_ENABLED not enabled
|
`else // TRACE_ENABLED not enabled
|
wire CRCErrorReport = ~(dbg_tb.i_tap_top.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
|
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.CHAIN_SELECTSelected | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RegisterScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.RiscDebugScanChain | dbg_tb.i_tap_top.DEBUGSelected & dbg_tb.i_tap_top.WishboneScanChain));
|
`endif
|
`endif
|
|
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
|
if(dbg_tb.i_tap_top.UpdateDR & ~dbg_tb.i_tap_top.IDCODESelected)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
else
|
else
|
if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(dbg_tb.i_tap_top.RegisterScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
else
|
else
|
if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(dbg_tb.i_tap_top.RiscDebugScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
if(dbg_tb.i_tap_top.WishboneScanChain & ~dbg_tb.i_tap_top.CHAIN_SELECTSelected)
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_tap_top.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LENGTH-1:0]);
|
|
|
if(CRCErrorReport)
|
if(CRCErrorReport)
|
begin
|
begin
|
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_tap_top.i_dbg_top.CalculatedCrcIn);
|
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
|
#1000 $stop;
|
#1000 $stop;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
| Line 841... |
Line 886... |
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.IDCODESelected)
|
if(dbg_tb.i_tap_top.IDCODESelected)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.ShiftDR)
|
if(dbg_tb.i_tap_top.ShiftDR)
|
TempData[31:0]<=#Tp {dbg_tb.i_tap_top.TDOData, TempData[31:1]};
|
TempData[31:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TempData[31:1]};
|
else
|
else
|
if(dbg_tb.i_tap_top.UpdateDR)
|
if(dbg_tb.i_tap_top.UpdateDR)
|
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
|
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
|
end
|
end
|
end
|
end
|
| Line 853... |
Line 898... |
|
|
// Print data from the trace buffer
|
// Print data from the trace buffer
|
reg [47:0] TraceData;
|
reg [47:0] TraceData;
|
always @ (posedge P_TCK)
|
always @ (posedge P_TCK)
|
begin
|
begin
|
if(dbg_tb.i_tap_top.DEBUGSelected & (dbg_tb.i_tap_top.i_dbg_top.Chain==`TRACE_TEST_CHAIN))
|
if(dbg_tb.i_tap_top.DEBUGSelected & (dbg_tb.i_dbg_top.Chain==`TRACE_TEST_CHAIN))
|
begin
|
begin
|
if(dbg_tb.i_tap_top.ShiftDR)
|
if(dbg_tb.i_tap_top.ShiftDR)
|
TraceData[47:0]<=#Tp {dbg_tb.i_tap_top.TDOData, TraceData[47:1]};
|
TraceData[47:0]<=#Tp {dbg_tb.i_tap_top.tdo_pad_o, TraceData[47:1]};
|
else
|
else
|
if(dbg_tb.i_tap_top.UpdateDR)
|
if(dbg_tb.i_tap_top.UpdateDR)
|
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
|
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
|
end
|
end
|
end
|
end
|
