| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.2 2001/09/18 14:12:43 mohor
|
|
// Trace fixed. Some registers changed, trace simplified.
|
|
//
|
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
|
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
|
// Initial official release.
|
// Initial official release.
|
//
|
//
|
// Revision 1.3 2001/06/01 22:23:40 mohor
|
// Revision 1.3 2001/06/01 22:23:40 mohor
|
// This is a backup. It is not a fully working version. Not for use, yet.
|
// This is a backup. It is not a fully working version. Not for use, yet.
|
| Line 207... |
Line 210... |
|
|
|
|
|
|
|
|
|
|
/* Anything starts trigger and qualifier
|
// Anything starts trigger and qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
|
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
|
// End: Anything starts trigger and qualifier */
|
|
|
|
|
|
// Anything starts trigger, breakpoint starts qualifier
|
|
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
|
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
#1000 WriteRegister(32'hffffffff, `RECSEL_ADR, 8'h78); // Two samples are selected for recording (RECSDATA and RECLDATA)
|
#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
|
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#100 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
wait(dbg_tb.dbgTAP1.TraceEnable)
|
// End: Anything starts trigger and qualifier //
|
@ (posedge Mclk);
|
|
#1 Bp = 1; // Set breakpoint
|
|
repeat(8) @(posedge Mclk);
|
/* Anything starts trigger, breakpoint starts qualifier
|
wait(dbg_tb.dbgTAP1.dbgTrace1.RiscStall)
|
#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
|
#1 Bp = 0; // Clear breakpoint
|
#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
|
// End: Anything starts trigger, breakpoint starts qualifier
|
#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
|
|
#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
|
|
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
|
|
wait(dbg_tb.dbgTAP1.TraceEnable)
|
|
@ (posedge Mclk);
|
|
#1 Bp = 1; // Set breakpoint
|
|
repeat(8) @(posedge Mclk);
|
|
wait(dbg_tb.dbgTAP1.dbgTrace1.RiscStall)
|
|
#1 Bp = 0; // Clear breakpoint
|
|
// End: Anything starts trigger, breakpoint starts qualifier */
|
|
|
|
|
/* Anything starts qualifier, breakpoint starts trigger
|
/* Anything starts qualifier, breakpoint starts trigger
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
|
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
|
#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
|
