| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.16 2004/01/05 12:16:50 mohor
|
|
// tmp2 version.
|
|
//
|
// Revision 1.15 2003/12/23 14:26:01 mohor
|
// Revision 1.15 2003/12/23 14:26:01 mohor
|
// New version of the debug interface. Not finished, yet.
|
// New version of the debug interface. Not finished, yet.
|
//
|
//
|
// Revision 1.14 2003/10/23 16:16:30 mohor
|
// Revision 1.14 2003/10/23 16:16:30 mohor
|
// CRC logic changed.
|
// CRC logic changed.
|
| Line 146... |
Line 149... |
wire [2:0] wb_cti_o;
|
wire [2:0] wb_cti_o;
|
wire [1:0] wb_bte_o;
|
wire [1:0] wb_bte_o;
|
|
|
// Text used for easier debugging
|
// Text used for easier debugging
|
reg [99:0] test_text;
|
reg [99:0] test_text;
|
|
reg [2:0] last_wb_cmd;
|
|
reg [99:0] last_wb_cmd_text;
|
|
reg [31:0] wb_data;
|
|
|
|
|
|
|
wire tdo_o;
|
wire tdo_o;
|
|
|
| Line 160... |
Line 165... |
|
|
reg test_enabled;
|
reg test_enabled;
|
|
|
reg [31:0] result;
|
reg [31:0] result;
|
|
|
|
reg [31:0] tmp_crc;
|
|
reg [31:0] shifted_in_crc;
|
|
|
wire tdo;
|
wire tdo;
|
|
|
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
|
assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
|
|
|
// Connecting TAP module
|
// Connecting TAP module
|
| Line 252... |
Line 260... |
|
|
// Initial values
|
// Initial values
|
initial
|
initial
|
begin
|
begin
|
test_enabled = 1'b0;
|
test_enabled = 1'b0;
|
|
wb_data = 32'h01234567;
|
trst_pad_i = 1'b1;
|
trst_pad_i = 1'b1;
|
tms_pad_i = 1'hz;
|
tms_pad_i = 1'hz;
|
tck_pad_i = 1'hz;
|
tck_pad_i = 1'hz;
|
tdi_pad_i = 1'hz;
|
tdi_pad_i = 1'hz;
|
|
|
| Line 311... |
Line 320... |
// #10000;
|
// #10000;
|
// xxx(4'b1001, 32'he579b242);
|
// xxx(4'b1001, 32'he579b242);
|
|
|
#10000;
|
#10000;
|
|
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 32'h0, 16'h4, 32'h08359131, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345678, 16'h4, 32'h57ecda62, result, "abc 1"); // {command, ready, addr, length, crc, result, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 32'h0, 16'h4, 32'hadfeabe2, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h12345679, 16'h4, 32'h563476e5, result, "abc 2"); // {command, ready, addr, length, crc, result, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 32'h0, 16'h4, 32'hd8b08283, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
// debug_wishbone(`WB_READ8, 1'b0, 32'h1234567a, 16'h4, 32'h545d836c, result, "abc 3"); // {command, ready, addr, length, crc, result, text}
|
|
//
|
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 32'h0, 16'h4, 32'haf07fce0, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 32'h86156251, result, "abc 4"); // {command, ready, addr, length, crc, result, text}
|
// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 32'h0, 16'h4, 32'h7f82ef52, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 32'h85a43b5f, result, "abc 5"); // {command, ready, addr, length, crc, result, text}
|
|
//
|
debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 32'h0, 16'h4, 32'h969b4113, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 32'hc9420a40, result, "abc"); // {command, ready, addr, length, crc, result, text}
|
|
//
|
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 32'h0, 16'h4, 32'h0accc633, result, "abc"); // {command, ready, addr, data, length, crc, result, text}
|
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 32'h87cdced6, result, "abc 6"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
// xxx(4'b1001, 32'he579b242);
|
// xxx(4'b1001, 32'he579b242);
|
|
|
wb_slave.cycle_response(`NO_RESPONSE, 8'h03, 8'h2); // (`NO_RESPONSE, wbs_waits, wbs_retries);
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 32'hc9420a40, result, "pac 1"); // {command, ready, addr, length, crc, result, text}
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 32'h0, 16'h4, 32'h969b4113, result, "pac 1"); // {command, ready, addr, data, length, crc, result, text}
|
|
|
|
#10000;
|
#10000;
|
wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result, "pac 2"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "pac 2"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
wb_slave.cycle_response(`ERR_RESPONSE, 8'h03, 8'h2); // (`NO_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ERR_RESPONSE, 8'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries);
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result, "pac 3"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "pac 3"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 32'h0, 16'h0, 32'haae8e1f9, result, "status 1"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 1"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 32'h0, 16'h0, 32'haae8e1f9, result, "status 2"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 2"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
wb_slave.cycle_response(`ACK_RESPONSE, 8'h4a, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 32'h0, 16'hc, 32'habaa5f3f, result, "rst_status"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "rst_status"); // {command, ready, addr, length, crc, result, text}
|
|
|
|
#10000;
|
|
debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "write 1"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 32'h0, 16'h4, 32'h2ec6ae56, result, "tre 8"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 32'hed029606, result, "write 16 bit len8"); // {command, ready, addr, length, crc, result, text}
|
|
|
#10000;
|
#10000;
|
debug_wishbone(`WB_GO, 1'b0, 32'h0, 32'h0, 16'h0, 32'haae8e1f9, result, "go 1"); // {command, ready, addr, data, length, crc, result, text}
|
debug_wishbone(`WB_WRITE8, 1'b0, 32'h12344446, 16'h8, 32'h3cfb2e35, result, "write 8 bit len8"); // {command, ready, addr, length, crc, result, text}
|
|
|
|
#10000;
|
|
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'h4c3fb42a, result, "go 1"); // {command, ready, addr, length, crc, result, text}
|
|
|
|
|
|
|
/*
|
/*
|
// Testing read and write to CPU0 registers
|
// Testing read and write to CPU0 registers
|
| Line 532... |
Line 546... |
|
|
task debug_wishbone;
|
task debug_wishbone;
|
input [2:0] command;
|
input [2:0] command;
|
input ready;
|
input ready;
|
input [31:0] addr;
|
input [31:0] addr;
|
input [31:0] data;
|
|
input [15:0] length;
|
input [15:0] length;
|
input [31:0] crc;
|
input [31:0] crc;
|
output [31:0] result;
|
output [31:0] result;
|
input [99:0] text;
|
input [99:0] text;
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
$write("(%0t) Task debug_wishbone: ", $time);
|
$write("(%0t) Task debug_wishbone: ", $time);
|
|
|
test_text = text;
|
test_text = text;
|
|
shifted_in_crc = crc;
|
|
|
case (command)
|
case (command)
|
`WB_STATUS :
|
`WB_STATUS :
|
begin
|
begin
|
// $display("wb_status (%0s)", text);
|
$display("wb_status (crc=0x%0x (%0s))", crc, text);
|
$display("wb_status (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
debug_wishbone_status(command, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
last_wb_cmd = `WB_STATUS; last_wb_cmd_text = "WB_STATUS";
|
end
|
end
|
`WB_READ8 :
|
`WB_READ8 :
|
begin
|
begin
|
$display("wb_read8 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
$display("wb_read8 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
|
last_wb_cmd = `WB_READ8; last_wb_cmd_text = "WB_READ8";
|
end
|
end
|
`WB_READ16 :
|
`WB_READ16 :
|
begin
|
begin
|
$display("wb_read16 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
$display("wb_read16 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
|
last_wb_cmd = `WB_READ16; last_wb_cmd_text = "WB_READ16";
|
end
|
end
|
`WB_READ32 :
|
`WB_READ32 :
|
begin
|
begin
|
$display("wb_read32 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
$display("wb_read32 (ready=%0d, adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", ready, addr, length, crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
|
last_wb_cmd = `WB_READ32; last_wb_cmd_text = "WB_READ32";
|
end
|
end
|
`WB_WRITE8 :
|
`WB_WRITE8 :
|
begin
|
begin
|
$display("wb_write8 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, data, length, crc, text);
|
$display("wb_write8 (adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, length, crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
|
last_wb_cmd = `WB_WRITE8; last_wb_cmd_text = "WB_WRITE8";
|
end
|
end
|
`WB_WRITE16 :
|
`WB_WRITE16 :
|
begin
|
begin
|
$display("wb_write16 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, data, length, crc, text);
|
$display("wb_write16 (adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, length, crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
|
last_wb_cmd = `WB_WRITE16; last_wb_cmd_text = "WB_WRITE16";
|
end
|
end
|
`WB_WRITE32 :
|
`WB_WRITE32 :
|
begin
|
begin
|
$display("wb_write32 (adr=0x%0x, data=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, data, length, crc, text);
|
$display("wb_write32 (adr=0x%0x, length=0x%0x, crc=0x%0x (%0s))", addr, length, crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
|
last_wb_cmd = `WB_WRITE32; last_wb_cmd_text = "WB_WRITE32";
|
end
|
end
|
`WB_GO :
|
`WB_GO :
|
begin
|
begin
|
$display("wb_go, crc=0x%0x (%0s))", crc, text);
|
$display("wb_go, crc=0x%0x (%0s))", crc, text);
|
debug_wishbone_set_addr(command, ready, addr, length, crc);
|
debug_wishbone_go(command, crc);
|
|
last_wb_cmd = `WB_GO; last_wb_cmd_text = "WB_GO";
|
end
|
end
|
endcase
|
endcase
|
|
|
|
|
|
|
|
|
end
|
end
|
endtask // debug_wishbone
|
endtask // debug_wishbone
|
|
|
|
|
|
|
| Line 618... |
Line 635... |
gen_clk(2); // we are in shiftDR
|
gen_clk(2); // we are in shiftDR
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
gen_clk(1);
|
gen_clk(1);
|
|
|
for(i=0; i<3; i=i+1)
|
for(i=2; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 command[i]; // command
|
tdi_pad_i<=#1 command[i]; // command
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=0; i<32; i=i+1) // address
|
for(i=31; i>=0; i=i-1) // address
|
begin
|
begin
|
tdi_pad_i<=#1 addr[i];
|
tdi_pad_i<=#1 addr[i];
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=0; i<16; i=i+1) // length
|
for(i=15; i>=0; i=i-1) // length
|
begin
|
begin
|
tdi_pad_i<=#1 length[i];
|
tdi_pad_i<=#1 length[i];
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
for(i=0; i<`CRC_LEN; i=i+1)
|
for(i=31; i>=0; i=i-1)
|
begin
|
begin
|
tdi_pad_i<=#1 crc[`CRC_LEN -1-i];
|
tdi_pad_i<=#1 crc[i];
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
if (wait_for_wb_ready)
|
if (wait_for_wb_ready)
|
begin
|
begin
|
| Line 664... |
Line 681... |
gen_clk(1); // to shift_dr
|
gen_clk(1); // to shift_dr
|
end
|
end
|
else
|
else
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
for(i=0; i<`CRC_LEN -1; i=i+1)
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
begin
|
begin
|
tdi_pad_i<=#1 1'b0;
|
tdi_pad_i<=#1 1'b0;
|
gen_clk(1);
|
gen_clk(1);
|
end
|
end
|
|
|
| Line 686... |
Line 703... |
|
|
|
|
|
|
|
|
|
|
|
task debug_wishbone_status;
|
|
input [2:0] command;
|
|
input [31:0] crc;
|
|
integer i;
|
|
|
|
begin
|
|
$display("(%0t) Task debug_wishbone_status: ", $time);
|
|
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1);
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(2); // we are in shiftDR
|
|
|
|
tdi_pad_i<=#1 1'b0; // chain_select bit = 0
|
|
gen_clk(1);
|
|
|
|
for(i=2; i>=0; i=i-1)
|
|
begin
|
|
tdi_pad_i<=#1 command[i]; // command
|
|
gen_clk(1);
|
|
end
|
|
|
|
for(i=31; i>=0; i=i-1) // crc
|
|
begin
|
|
tdi_pad_i<=#1 crc[i];
|
|
gen_clk(1);
|
|
end
|
|
|
|
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
|
|
|
// Reads sample from the Trace Buffer
|
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
|
task ReadTraceBuffer;
|
|
begin
|
begin
|
$display("(%0t) Task ReadTraceBuffer", $time);
|
tdi_pad_i<=#1 1'b0;
|
|
gen_clk(1);
|
|
end
|
|
|
|
tdi_pad_i<=#1 crc[i]; // last crc
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1); // to exit1_dr
|
|
|
|
tdi_pad_i<=#1 'hz; // tri-state
|
|
tms_pad_i<=#1 1;
|
|
gen_clk(1); // to update_dr
|
|
tms_pad_i<=#1 0;
|
|
gen_clk(1); // to run_test_idle
|
|
end
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endtask // debug_wishbone_status
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task debug_wishbone_go;
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input [2:0] command;
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input [31:0] crc;
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integer i, j;
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begin
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$display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
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tms_pad_i<=#1 1;
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tms_pad_i<=#1 1;
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gen_clk(1);
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gen_clk(1);
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(2); // we are in shiftDR
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gen_clk(2); // we are in shiftDR
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tdi_pad_i<=#1 0;
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tdi_pad_i<=#1 1'b0; // chain_select bit = 0
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gen_clk(47);
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tms_pad_i<=#1 1; // going out of shiftIR
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gen_clk(1);
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gen_clk(1);
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tdi_pad_i<=#1 'hz; // tri-state
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for(i=2; i>=0; i=i-1)
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begin
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tdi_pad_i<=#1 command[i]; // command
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gen_clk(1);
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gen_clk(1);
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end
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if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted.
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begin
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for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+32)
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begin
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$display("wb_data = 0x%x", wb_data);
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for (j=31; j>=0; j=j-1)
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begin
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tdi_pad_i<=#1 wb_data[j];
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gen_clk(1);
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end
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wb_data = wb_data + 32'h11111111;
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end
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end
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for(i=31; i>=0; i=i-1) // crc
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begin
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tdi_pad_i<=#1 crc[i];
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gen_clk(1);
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end
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gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
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for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
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begin
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tdi_pad_i<=#1 1'b0;
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gen_clk(1);
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end
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tdi_pad_i<=#1 crc[i]; // last crc
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tms_pad_i<=#1 1;
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gen_clk(1); // to exit1_dr
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tdi_pad_i<=#1 'hz; // tri-state
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tms_pad_i<=#1 1;
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gen_clk(1); // to update_dr
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tms_pad_i<=#1 0;
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tms_pad_i<=#1 0;
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gen_clk(1); // we are in RunTestIdle
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gen_clk(1); // to run_test_idle
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end
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end
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endtask
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endtask // debug_wishbone_go
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// Reads the CPU register and latches the data so it is ready for reading
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// Reads the CPU register and latches the data so it is ready for reading
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task ReadCPURegister;
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task ReadCPURegister;
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input [31:0] Address;
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input [31:0] Address;
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| Line 1128... |
Line 1244... |
gen_clk(1); // to run_test_idle
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gen_clk(1); // to run_test_idle
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end
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end
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endtask
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endtask
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// Printing CRC
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//always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end)
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always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or posedge dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end)
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begin
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#2;
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if (dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end & dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end)
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tmp_crc = dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc;
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end
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// Detecting CRC error
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always @ (posedge dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_end)
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begin
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#2;
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if (~dbg_tb.i_dbg_top.crc_match)
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begin
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$display("\t\tCRC ERROR !!!");
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$display("\t\tCRC needed (%0s) = 0x%0x , shifted_in = 0x%0x", test_text, tmp_crc, shifted_in_crc);
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end
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end
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endmodule // dbg_tb
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endmodule // dbg_tb
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No newline at end of file
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No newline at end of file
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