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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Diff between revs 93 and 95

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Rev 93 Rev 95
Line 41... Line 41...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.22  2004/01/13 11:28:30  mohor
 
// tmp version.
 
//
// Revision 1.21  2004/01/10 07:50:41  mohor
// Revision 1.21  2004/01/10 07:50:41  mohor
// temp version.
// temp version.
//
//
// Revision 1.20  2004/01/09 12:49:23  mohor
// Revision 1.20  2004/01/09 12:49:23  mohor
// tmp version.
// tmp version.
Line 219... Line 222...
 
 
               );
               );
 
 
 
 
dbg_top i_dbg_top  (
dbg_top i_dbg_top  (
 
 
                    .trst_i(!trst_pad_i),
 
                    .tck_i(tck_pad_i),
                    .tck_i(tck_pad_i),
                    .tdi_i(tdo_o),
                    .tdi_i(tdo_o),
                    .tdo_o(debug_tdi_i),
                    .tdo_o(debug_tdi_i),
 
 
                    // TAP states
                    // TAP states
Line 318... Line 319...
  $display("//////////////////////////////////////////////////////////////////");
  $display("//////////////////////////////////////////////////////////////////");
 
 
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
  initialize_memory(32'h12340000, 32'h00100000);  // Initialize 0x100000 bytes starting from address 0x12340000
 
 
  reset_tap;
  reset_tap;
 
 
 
  #500;
  goto_run_test_idle;
  goto_run_test_idle;
 
 
  // Testing read and write to internal registers
  // Testing read and write to internal registers
  #10000;
  #10000;
  set_instruction(`IDCODE);
  set_instruction(`IDCODE);
Line 408... Line 411...
 
 
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
  ReadCPURegister(32'h11001100, 8'hdb);                 // {addr, crc}
*/
*/
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
  #5000 gen_clk(1);            // One extra TCLK for debugging purposes
 
  $display("\n\nSimulation end.");
  #1000 $stop;
  #1000 $stop;
 
 
end
end
 
 
 
 
Line 448... Line 452...
// TAP reset
// TAP reset
task reset_tap;
task reset_tap;
  begin
  begin
    $display("(%0t) Task reset_tap", $time);
    $display("(%0t) Task reset_tap", $time);
    tms_pad_i<=#1 1'b1;
    tms_pad_i<=#1 1'b1;
    gen_clk(7);
    gen_clk(5);
  end
  end
endtask
endtask
 
 
 
 
// Goes to RunTestIdle state
// Goes to RunTestIdle state
Line 832... Line 836...
 
 
 
 
 
 
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_WRITEx was previously activated, data needs to be shifted.
    if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32))  // When WB_WRITEx was previously activated, data needs to be shifted.
      begin
      begin
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.len << 3, dbg_tb.i_dbg_top.i_dbg_wb.len);
        $display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit, dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit>>3);
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
        for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_limit); i=i+1)
          gen_clk(1);
          gen_clk(1);
      end
      end
 
 
 
 
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.
    gen_clk(`STATUS_LEN);   // Generating 4 clocks to read out status.

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