| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2004/01/17 18:38:11 mohor
|
|
// cpu_tall_o is set with cpu_stb_o or register.
|
|
//
|
// Revision 1.3 2004/01/17 18:01:24 mohor
|
// Revision 1.3 2004/01/17 18:01:24 mohor
|
// New version.
|
// New version.
|
//
|
//
|
// Revision 1.2 2004/01/17 17:01:14 mohor
|
// Revision 1.2 2004/01/17 17:01:14 mohor
|
// Almost finished.
|
// Almost finished.
|
| Line 127... |
Line 130... |
output cpu_rst_o;
|
output cpu_rst_o;
|
|
|
|
|
|
|
reg tdo_o;
|
reg tdo_o;
|
reg [799:0] tdo_text;
|
|
|
|
wire cmd_cnt_en;
|
wire cmd_cnt_en;
|
reg [1:0] cmd_cnt;
|
reg [1:0] cmd_cnt;
|
wire cmd_cnt_end;
|
wire cmd_cnt_end;
|
reg cmd_cnt_end_q;
|
reg cmd_cnt_end_q;
|
| Line 149... |
Line 151... |
wire data_cnt_end;
|
wire data_cnt_end;
|
reg data_cnt_end_q;
|
reg data_cnt_end_q;
|
wire status_cnt_end;
|
wire status_cnt_end;
|
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
|
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
|
reg [3:0] status;
|
reg [3:0] status;
|
reg [199:0] status_text;
|
|
|
|
reg crc_match_reg;
|
reg crc_match_reg;
|
wire enable;
|
wire enable;
|
|
|
reg read_cycle_reg;
|
reg read_cycle_reg;
|
| Line 191... |
Line 192... |
reg cycle_32_bit;
|
reg cycle_32_bit;
|
reg reg_access;
|
reg reg_access;
|
|
|
reg [31:0] adr;
|
reg [31:0] adr;
|
reg set_addr;
|
reg set_addr;
|
reg [199:0] latching_data_text;
|
|
reg cpu_ack_sync;
|
reg cpu_ack_sync;
|
reg cpu_ack_tck;
|
reg cpu_ack_tck;
|
reg cpu_ack_tck_q;
|
reg cpu_ack_tck_q;
|
reg cpu_stb;
|
reg cpu_stb;
|
reg cpu_stb_sync;
|
reg cpu_stb_sync;
|
| Line 217... |
Line 217... |
|
|
// Command counter
|
// Command counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
cmd_cnt <= #1 'h0;
|
cmd_cnt <= #1 2'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
cmd_cnt <= #1 'h0;
|
cmd_cnt <= #1 2'h0;
|
else if (cmd_cnt_en)
|
else if (cmd_cnt_en)
|
cmd_cnt <= #1 cmd_cnt + 1'b1;
|
cmd_cnt <= #1 cmd_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
| Line 232... |
Line 232... |
|
|
// Address/length counter
|
// Address/length counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
addr_cnt <= #1 'h0;
|
addr_cnt <= #1 6'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
addr_cnt <= #1 'h0;
|
addr_cnt <= #1 6'h0;
|
else if (addr_cnt_en)
|
else if (addr_cnt_en)
|
addr_cnt <= #1 addr_cnt + 1'b1;
|
addr_cnt <= #1 addr_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
| Line 247... |
Line 247... |
|
|
// Data counter
|
// Data counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 6'h0;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
data_cnt <= #1 'h0;
|
data_cnt <= #1 6'h0;
|
else if (data_cnt_en)
|
else if (data_cnt_en)
|
data_cnt <= #1 data_cnt + 1'b1;
|
data_cnt <= #1 data_cnt + 1'b1;
|
end
|
end
|
|
|
|
|
| Line 262... |
Line 262... |
|
|
// crc counter
|
// crc counter
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 6'h0;
|
else if(crc_cnt_en)
|
else if(crc_cnt_en)
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
crc_cnt <= #1 crc_cnt + 1'b1;
|
else if (update_dr_i)
|
else if (update_dr_i)
|
crc_cnt <= #1 'h0;
|
crc_cnt <= #1 6'h0;
|
end
|
end
|
|
|
|
|
// Upper limit. Address/length counter counts until this value is reached
|
// Upper limit. Address/length counter counts until this value is reached
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
| Line 364... |
Line 364... |
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (reg_access)
|
if (reg_access)
|
begin
|
begin
|
dr[31:24] <= #1 reg_data_out;
|
dr[31:24] <= #1 reg_data_out;
|
latching_data_text = "Latch reg data";
|
|
end
|
end
|
else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
|
else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu)
|
begin
|
begin
|
if (cycle_32_bit)
|
if (cycle_32_bit)
|
dr[31:0] <= #1 cpu_data_i;
|
dr[31:0] <= #1 cpu_data_i;
|
else
|
else
|
dr[31:24] <= #1 cpu_data_i[7:0];
|
dr[31:24] <= #1 cpu_data_i[7:0];
|
latching_data_text = "Latch cpu data";
|
|
end
|
end
|
else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
|
else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle)))
|
begin
|
begin
|
dr <= #1 {dr[33:0], tdi_i};
|
dr <= #1 {dr[33:0], tdi_i};
|
latching_data_text = "shifting data";
|
|
end
|
end
|
else
|
|
latching_data_text = "nothing";
|
|
end
|
end
|
|
|
|
|
assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
|
assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
|
assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
|
assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
|
| Line 590... |
Line 585... |
// Status register
|
// Status register
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
status <= #1 'h0;
|
status <= #1 4'h0;
|
status_text <= #1 "reset";
|
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
|
begin
|
begin
|
status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
|
status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0};
|
status_text <= #1 "!!!READ";
|
|
end
|
end
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
|
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
|
begin
|
begin
|
status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
|
status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0};
|
status_text <= #1 "READ";
|
|
end
|
end
|
else if (shift_dr_i & (~status_cnt_end))
|
else if (shift_dr_i & (~status_cnt_end))
|
begin
|
begin
|
status <= #1 {status[0], status[3:1]};
|
status <= #1 {status[0], status[3:1]};
|
status_text <= #1 "shift";
|
|
end
|
end
|
end
|
end
|
// Following status is shifted out:
|
// Following status is shifted out:
|
// 1. bit: 1 if crc is OK, else 0
|
// 1. bit: 1 if crc is OK, else 0
|
// 2. bit: 1'b0
|
// 2. bit: 1'b0
|
| Line 624... |
Line 615... |
read_cycle or crc_match_reg or status or dr)
|
read_cycle or crc_match_reg or status or dr)
|
begin
|
begin
|
if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
tdo_text = "crc_match_i";
|
|
end
|
end
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
begin
|
begin
|
tdo_o = dr[31];
|
tdo_o = dr[31];
|
tdo_text = "read data";
|
|
end
|
end
|
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
|
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
|
begin
|
begin
|
tdo_o = crc_match_reg;
|
tdo_o = crc_match_reg;
|
tdo_text = "crc_match_reg";
|
|
end
|
end
|
else if (crc_cnt_end)
|
else if (crc_cnt_end)
|
begin
|
begin
|
tdo_o = status[0];
|
tdo_o = status[0];
|
tdo_text = "status";
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tdo_o = 1'b0;
|
tdo_o = 1'b0;
|
tdo_text = "zero while CRC is shifted in";
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
