| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.28 2002/11/06 14:22:41 mohor
|
|
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
|
|
//
|
// Revision 1.27 2002/10/10 02:42:55 mohor
|
// Revision 1.27 2002/10/10 02:42:55 mohor
|
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
|
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.
|
//
|
//
|
// Revision 1.26 2002/05/07 14:43:59 mohor
|
// Revision 1.26 2002/05/07 14:43:59 mohor
|
// mon_cntl_o signals that controls monitor mux added.
|
// mon_cntl_o signals that controls monitor mux added.
|
| Line 151... |
Line 154... |
// Top module
|
// Top module
|
module dbg_top(
|
module dbg_top(
|
|
|
// RISC signals
|
// RISC signals
|
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
|
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
|
bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
|
bp_i, opselect_o, lsstatus_i, istatus_i,
|
|
risc_stall_o, risc_stall_all_o, risc_sel_o, reset_o,
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
wb_rst_i, wb_clk_i,
|
wb_rst_i, wb_clk_i,
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
| Line 189... |
Line 193... |
input [3:0] lsstatus_i; // Load/store status inputs
|
input [3:0] lsstatus_i; // Load/store status inputs
|
input [1:0] istatus_i; // Instruction status inputs
|
input [1:0] istatus_i; // Instruction status inputs
|
output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
|
output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
|
output [31:0] risc_data_o; // RISC data output (data read from risc registers)
|
output [31:0] risc_data_o; // RISC data output (data read from risc registers)
|
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
output risc_stall_o; // Stalls the RISC
|
output risc_stall_o; // Stalls the selected RISC
|
|
output risc_stall_all_o; // Stalls all the rest RISCs
|
|
output [`RISC_NUM-1:0] risc_sel_o; // Stalls all the rest RISCs
|
output reset_o; // Resets the RISC
|
output reset_o; // Resets the RISC
|
|
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
input wb_rst_i; // WISHBONE reset
|
input wb_rst_i; // WISHBONE reset
|
| Line 248... |
Line 254... |
|
|
reg RegAccess_q; // Delayed signals used for accessing the registers
|
reg RegAccess_q; // Delayed signals used for accessing the registers
|
reg RegAccess_q2; // Delayed signals used for accessing the registers
|
reg RegAccess_q2; // Delayed signals used for accessing the registers
|
reg RISCAccess_q; // Delayed signals used for accessing the RISC
|
reg RISCAccess_q; // Delayed signals used for accessing the RISC
|
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
|
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
|
|
reg RISCAccess_q3; // Delayed signals used for accessing the RISC
|
|
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
reg WBInProgress; // WISHBONE access is in progress
|
reg WBInProgress; // WISHBONE access is in progress
|
| Line 645... |
Line 652... |
begin
|
begin
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
|
RISCAccess_q3 <=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q <=#Tp RegAccess;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RegAccess_q2 <=#Tp RegAccess_q;
|
RISCAccess_q <=#Tp RISCAccess;
|
RISCAccess_q <=#Tp RISCAccess;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
RISCAccess_q2 <=#Tp RISCAccess_q;
|
|
RISCAccess_q3 <=#Tp RISCAccess_q2;
|
end
|
end
|
end
|
end
|
|
|
// Chip select and read/write signals for accessing RISC
|
// Chip select and read/write signals for accessing RISC
|
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
|
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q2 & RW;
|
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
|
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
|
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
|
assign RiscStall_access = RISCAccess & ~RISCAccess_q3;
|
|
|
|
|
reg wb_Access_wbClk_q;
|
reg wb_Access_wbClk_q;
|
// Delayed signals used for accessing WISHBONE
|
// Delayed signals used for accessing WISHBONE
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
| Line 888... |
Line 897... |
.IQualifValid(IQualifValid),
|
.IQualifValid(IQualifValid),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
|
`endif
|
`endif
|
.risc_stall(RiscStall_reg), .risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
|
.risc_stall(RiscStall_reg), .risc_stall_all(risc_stall_all_o), .risc_sel(risc_sel_o),
|
|
.risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
|
|
|
);
|
);
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
