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Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.35 2004/01/14 22:59:16 mohor
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// Temp version.
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//
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// Revision 1.34 2003/12/23 15:07:34 mohor
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// Revision 1.34 2003/12/23 15:07:34 mohor
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// New directory structure. New version of the debug interface.
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// New directory structure. New version of the debug interface.
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// Files that are not needed removed.
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// Files that are not needed removed.
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//
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//
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// Revision 1.33 2003/10/23 16:17:01 mohor
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// Revision 1.33 2003/10/23 16:17:01 mohor
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| Line 233... |
Line 236... |
reg [`CRC_CNT -1:0] crc_cnt;
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reg [`CRC_CNT -1:0] crc_cnt;
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reg [`STATUS_CNT -1:0] status_cnt;
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reg [`STATUS_CNT -1:0] status_cnt;
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reg [`CHAIN_DATA_LEN -1:0] chain_dr;
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reg [`CHAIN_DATA_LEN -1:0] chain_dr;
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reg [`CHAIN_ID_LENGTH -1:0] chain;
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reg [`CHAIN_ID_LENGTH -1:0] chain;
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wire chain_latch_en;
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wire data_cnt_end;
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wire data_cnt_end;
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wire crc_cnt_end;
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wire crc_cnt_end;
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wire status_cnt_end;
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wire status_cnt_end;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q;
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reg crc_cnt_end_q2;
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reg crc_cnt_end_q2;
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| Line 244... |
Line 248... |
reg chain_select;
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reg chain_select;
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reg chain_select_error;
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reg chain_select_error;
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wire crc_out;
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wire crc_out;
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wire crc_match;
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wire crc_match;
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wire crc_en_wb;
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wire crc_en_wb;
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wire crc_en_cpu;
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wire shift_crc_wb;
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wire shift_crc_wb;
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wire shift_crc_cpu;
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wire data_shift_en;
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wire data_shift_en;
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wire selecting_command;
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wire selecting_command;
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reg tdo_o;
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reg tdo_o;
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reg wishbone_ce;
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reg wishbone_ce;
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reg cpu_ce;
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wire tdi_wb;
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wire tdi_cpu;
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wire tdo_wb;
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wire tdo_cpu;
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wire shift_crc;
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// data counter
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// data counter
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always @ (posedge tck_i or posedge wb_rst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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| Line 331... |
Line 346... |
default : chain_select_error <= #1 1'b1;
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default : chain_select_error <= #1 1'b1;
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endcase
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endcase
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end
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end
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assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q);
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always @ (posedge tck_i or posedge wb_rst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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chain <= `CHAIN_ID_LENGTH'b111;
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chain <= `CHAIN_ID_LENGTH'b111;
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else if(chain_select & crc_cnt_end & (~crc_cnt_end_q) & crc_match)
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else if(chain_latch_en & crc_match)
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chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
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chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1];
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end
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end
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assign data_shift_en = shift_dr_i & (~data_cnt_end);
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assign data_shift_en = shift_dr_i & (~data_cnt_end);
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| Line 368... |
Line 386... |
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reg tdo_chain_select;
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reg tdo_chain_select;
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wire crc_en;
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wire crc_en;
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wire crc_en_dbg;
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wire crc_en_dbg;
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reg crc_started;
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reg crc_started;
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assign crc_en = crc_en_dbg | crc_en_wb;
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assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu;
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assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
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assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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begin
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begin
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if (crc_en)
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if (crc_en)
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| Line 433... |
Line 451... |
end
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end
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endcase
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endcase
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end
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end
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wire tdi_wb;
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wire tdo_wb;
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always @ (shift_crc_wb or crc_out or wishbone_ce or tdo_wb or tdo_chain_select)
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assign shift_crc = shift_crc_wb | shift_crc_cpu;
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always @ (shift_crc or crc_out or wishbone_ce or tdo_wb or tdo_cpu or tdo_chain_select)
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begin
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begin
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if (shift_crc_wb) // shifting crc
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if (shift_crc) // shifting crc
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tdo_tmp = crc_out;
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tdo_tmp = crc_out;
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else if (wishbone_ce) // shifting data from wb
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else if (wishbone_ce) // shifting data from wb
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tdo_tmp = tdo_wb;
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tdo_tmp = tdo_wb;
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else if (cpu_ce) // shifting data from cpu
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tdo_tmp = tdo_cpu;
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else
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else
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tdo_tmp = tdo_chain_select;
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tdo_tmp = tdo_chain_select;
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end
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end
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| Line 461... |
Line 482... |
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always @ (posedge tck_i or posedge wb_rst_i)
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always @ (posedge tck_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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wishbone_ce <= #1 1'b0;
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wishbone_ce <= #1 1'b0;
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else if(selecting_command & (~tdi_i) & wishbone_scan_chain) // wishbone CE
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cpu_ce <= #1 1'b0;
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end
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else if(selecting_command & (~tdi_i))
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begin
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if (wishbone_scan_chain) // wishbone CE
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wishbone_ce <= #1 1'b1;
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wishbone_ce <= #1 1'b1;
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if (cpu_debug_scan_chain) // CPU CE
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cpu_ce <= #1 1'b1;
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end
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else if (update_dr_i) // igor !!! This needs to be changed?
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else if (update_dr_i) // igor !!! This needs to be changed?
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begin
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wishbone_ce <= #1 1'b0;
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wishbone_ce <= #1 1'b0;
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cpu_ce <= #1 1'b0;
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end
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end
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end
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assign tdi_wb = wishbone_ce & tdi_i;
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assign tdi_wb = wishbone_ce & tdi_i;
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assign tdi_cpu = cpu_ce & tdi_i;
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// Connecting wishbone module
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// Connecting wishbone module
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dbg_wb i_dbg_wb (
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dbg_wb i_dbg_wb (
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// JTAG signals
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// JTAG signals
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.tck_i (tck_i),
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.tck_i (tck_i),
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| Line 505... |
Line 539... |
.wb_ack_i (wb_ack_i),
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.wb_ack_i (wb_ack_i),
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.wb_cab_o (wb_cab_o),
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.wb_cab_o (wb_cab_o),
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.wb_err_i (wb_err_i),
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.wb_err_i (wb_err_i),
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.wb_cti_o (wb_cti_o),
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.wb_cti_o (wb_cti_o),
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.wb_bte_o (wb_bte_o)
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.wb_bte_o (wb_bte_o)
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);
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// Connecting cpu module
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dbg_cpu i_dbg_cpu (
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// JTAG signals
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.tck_i (tck_i),
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.tdi_i (tdi_cpu),
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.tdo_o (tdo_cpu),
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// TAP states
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.shift_dr_i (shift_dr_i),
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.pause_dr_i (pause_dr_i),
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.update_dr_i (update_dr_i),
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.cpu_ce_i (cpu_ce),
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.crc_match_i (crc_match),
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.crc_en_o (crc_en_cpu),
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.shift_crc_o (shift_crc_cpu),
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.rst_i (wb_rst_i),
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.clk_i (wb_clk_i)
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);
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);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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