| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2004/01/17 18:01:24 mohor
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// New version.
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//
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// Revision 1.14 2004/01/16 14:51:33 mohor
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// Revision 1.14 2004/01/16 14:51:33 mohor
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// cpu registers added.
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// cpu registers added.
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//
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//
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// Revision 1.13 2004/01/15 12:09:43 mohor
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// Revision 1.13 2004/01/15 12:09:43 mohor
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// Working.
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// Working.
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| Line 226... |
Line 229... |
reg wb_end_rst;
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reg wb_end_rst;
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reg wb_end_rst_sync;
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reg wb_end_rst_sync;
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reg wb_end_sync;
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reg wb_end_sync;
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reg wb_end_tck, wb_end_tck_q;
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reg wb_end_tck, wb_end_tck_q;
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reg busy_sync;
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reg busy_sync;
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reg [799:0] tdo_text;
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reg [399:0] latching_data_text;
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reg latch_data;
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reg latch_data;
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reg [199:0] status_text;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
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reg read_cycle;
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reg read_cycle;
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reg write_cycle;
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reg write_cycle;
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reg [2:0] rw_type;
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reg [2:0] rw_type;
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| Line 276... |
Line 276... |
begin
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begin
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if (read_cycle & crc_cnt_31)
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if (read_cycle & crc_cnt_31)
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begin
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begin
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dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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latching_data_text <= #1 "First latch";
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end
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end
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else if (read_cycle & crc_cnt_end)
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else if (read_cycle & crc_cnt_end)
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begin
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begin
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case (rw_type) // synthesis parallel_case full_case
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case (rw_type) // synthesis parallel_case full_case
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`WB_READ8 : begin
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`WB_READ8 : begin
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| Line 291... |
Line 290... |
2'b01 : dr[31:24] <= #1 input_data[23:16];
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2'b01 : dr[31:24] <= #1 input_data[23:16];
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2'b10 : dr[31:24] <= #1 input_data[15:8];
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2'b10 : dr[31:24] <= #1 input_data[15:8];
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2'b11 : dr[31:24] <= #1 input_data[7:0];
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2'b11 : dr[31:24] <= #1 input_data[7:0];
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endcase
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endcase
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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latching_data_text <= #1 "8 bit latched";
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end
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end
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else
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else
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begin
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begin
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dr[31:24] <= #1 {dr[30:24], 1'b0};
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dr[31:24] <= #1 {dr[30:24], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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latching_data_text <= #1 "8 bit shifted";
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end
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end
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end
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end
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`WB_READ16: begin
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`WB_READ16: begin
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if(half & (~half_q))
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if(half & (~half_q))
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begin
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begin
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if (ptr[1])
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if (ptr[1])
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dr[31:16] <= #1 input_data[15:0];
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dr[31:16] <= #1 input_data[15:0];
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else
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else
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dr[31:16] <= #1 input_data[31:16];
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dr[31:16] <= #1 input_data[31:16];
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latching_data_text <= #1 "16 bit latched";
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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dr[31:16] <= #1 {dr[30:16], 1'b0};
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dr[31:16] <= #1 {dr[30:16], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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latching_data_text <= #1 "16 bit shifted";
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end
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end
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end
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end
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`WB_READ32: begin
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`WB_READ32: begin
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if(long & (~long_q))
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if(long & (~long_q))
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begin
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begin
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dr[31:0] <= #1 input_data[31:0];
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dr[31:0] <= #1 input_data[31:0];
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latch_data <= #1 1'b1;
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latch_data <= #1 1'b1;
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latching_data_text <= #1 "32 bit latched";
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end
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end
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else
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else
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begin
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begin
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dr[31:0] <= #1 {dr[30:0], 1'b0};
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dr[31:0] <= #1 {dr[30:0], 1'b0};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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latching_data_text <= #1 "32 bit shifted";
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
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else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
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begin
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begin
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dr <= #1 {dr[49:0], tdi_i};
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dr <= #1 {dr[49:0], tdi_i};
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latch_data <= #1 1'b0;
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latch_data <= #1 1'b0;
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latching_data_text <= #1 "tdi shifted in";
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end
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end
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else
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latching_data_text <= #1 "nothing";
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end
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end
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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assign cmd_cnt_en = enable & (~cmd_cnt_end);
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// Command counter
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// Command counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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cmd_cnt <= #1 'h0;
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cmd_cnt <= #1 2'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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cmd_cnt <= #1 'h0;
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cmd_cnt <= #1 2'h0;
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else if (cmd_cnt_en)
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else if (cmd_cnt_en)
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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cmd_cnt <= #1 cmd_cnt + 1'b1;
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end
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end
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| Line 366... |
Line 356... |
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// Address/length counter
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// Address/length counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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addr_len_cnt <= #1 'h0;
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addr_len_cnt <= #1 6'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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addr_len_cnt <= #1 'h0;
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addr_len_cnt <= #1 6'h0;
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else if (addr_len_cnt_en)
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else if (addr_len_cnt_en)
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addr_len_cnt <= #1 addr_len_cnt + 1'b1;
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addr_len_cnt <= #1 addr_len_cnt + 1'b1;
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end
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end
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| Line 381... |
Line 371... |
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// Data counter
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// Data counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 19'h0;
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else if (update_dr_i)
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else if (update_dr_i)
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data_cnt <= #1 'h0;
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data_cnt <= #1 19'h0;
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else if (data_cnt_en)
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else if (data_cnt_en)
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data_cnt <= #1 data_cnt + 1'b1;
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data_cnt <= #1 data_cnt + 1'b1;
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end
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end
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| Line 406... |
Line 396... |
half_q2 <= #1 half_q;
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half_q2 <= #1 half_q;
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long_q2 <= #1 long_q;
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long_q2 <= #1 long_q;
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end
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end
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assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
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assign dr_read = (dr[2:0] == `WB_READ8) || (dr[2:0] == `WB_READ16) || (dr[2:0] == `WB_READ32);
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assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
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assign dr_write = (dr[2:0] == `WB_WRITE8) || (dr[2:0] == `WB_WRITE16) || (dr[2:0] == `WB_WRITE32);
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assign dr_go = dr[2:0] == `WB_GO;
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assign dr_go = dr[2:0] == `WB_GO;
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// Latching instruction
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// Latching instruction
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always @ (posedge tck_i)
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always @ (posedge tck_i)
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| Line 462... |
Line 452... |
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// crc counter
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// crc counter
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 6'h0;
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else if(crc_cnt_en)
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else if(crc_cnt_en)
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crc_cnt <= #1 crc_cnt + 1'b1;
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crc_cnt <= #1 crc_cnt + 1'b1;
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else if (update_dr_i)
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else if (update_dr_i)
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crc_cnt <= #1 'h0;
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crc_cnt <= #1 6'h0;
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end
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end
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|
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign cmd_cnt_end = cmd_cnt == 2'h3;
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assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
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assign crc_cnt_end = crc_cnt == 6'd32;
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assign crc_cnt_end = crc_cnt == 6'd32;
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| Line 528... |
Line 518... |
// Status register
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// Status register
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
|
begin
|
status <= #1 'h0;
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status <= #1 {`STATUS_LEN{1'b0}};
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status_text <= #1 "reset";
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end
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end
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
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begin
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begin
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status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
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status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
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status_text <= #1 "!!!READ";
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end
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end
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
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else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
|
begin
|
begin
|
status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
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status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
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status_text <= #1 "READ";
|
|
end
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end
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else if (shift_dr_i & (~status_cnt_end))
|
else if (shift_dr_i & (~status_cnt_end))
|
begin
|
begin
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
|
status_text <= #1 "shift";
|
|
end
|
end
|
end
|
end
|
// Following status is shifted out:
|
// Following status is shifted out:
|
// 1. bit: 1 if crc is OK, else 0
|
// 1. bit: 1 if crc is OK, else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
// 2. bit: 1 while WB access is in progress (busy_tck), else 0
|
| Line 562... |
Line 548... |
data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr)
|
data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr)
|
begin
|
begin
|
if (pause_dr_i)
|
if (pause_dr_i)
|
begin
|
begin
|
tdo_o = busy_tck;
|
tdo_o = busy_tck;
|
tdo_text = "busy_tck";
|
|
end
|
end
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
|
begin
|
begin
|
tdo_o = crc_match_i;
|
tdo_o = crc_match_i;
|
tdo_text = "crc_match_i";
|
|
end
|
end
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
else if (read_cycle & crc_cnt_end & (~data_cnt_end))
|
begin
|
begin
|
tdo_o = dr[31];
|
tdo_o = dr[31];
|
tdo_text = "read data";
|
|
end
|
end
|
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
|
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
|
begin
|
begin
|
tdo_o = crc_match_reg;
|
tdo_o = crc_match_reg;
|
tdo_text = "crc_match_reg";
|
|
end
|
end
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
else if (crc_cnt_end & data_cnt_end) // cmd is already updated
|
begin
|
begin
|
tdo_o = status[0];
|
tdo_o = status[0];
|
tdo_text = "status";
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tdo_o = 1'b0;
|
tdo_o = 1'b0;
|
tdo_text = "zero while CRC is shifted in";
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
| Line 605... |
Line 585... |
// Latching instruction
|
// Latching instruction
|
always @ (posedge tck_i or posedge rst_i)
|
always @ (posedge tck_i or posedge rst_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
cmd <= #1 'h0;
|
cmd <= #1 3'h0;
|
cmd_old <= #1 'h0;
|
cmd_old <= #1 3'h0;
|
cmd_read <= #1 1'b0;
|
cmd_read <= #1 1'b0;
|
cmd_write <= #1 1'b0;
|
cmd_write <= #1 1'b0;
|
cmd_go <= #1 1'b0;
|
cmd_go <= #1 1'b0;
|
end
|
end
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
|
| Line 960... |
Line 940... |
|
|
// Logic for latching data that is read from wishbone
|
// Logic for latching data that is read from wishbone
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if(wishbone_ce_rst)
|
if(wishbone_ce_rst)
|
mem_ptr <= #1 'h0;
|
mem_ptr <= #1 3'h0;
|
else if (wb_ack_i)
|
else if (wb_ack_i)
|
begin
|
begin
|
if (rw_type == `WB_READ8)
|
if (rw_type == `WB_READ8)
|
mem_ptr <= #1 mem_ptr + 1'd1;
|
mem_ptr <= #1 mem_ptr + 1'd1;
|
else if (rw_type == `WB_READ16)
|
else if (rw_type == `WB_READ16)
|
| Line 1011... |
Line 991... |
|
|
// Fifo counter and empty/full detection
|
// Fifo counter and empty/full detection
|
always @ (posedge tck_i)
|
always @ (posedge tck_i)
|
begin
|
begin
|
if (update_dr_i)
|
if (update_dr_i)
|
fifo_cnt <= #1 'h0;
|
fifo_cnt <= #1 3'h0;
|
else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing
|
else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing
|
begin
|
begin
|
case (rw_type) // synthesis parallel_case full_case
|
case (rw_type) // synthesis parallel_case full_case
|
`WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
|
`WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
|
`WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
|
`WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
|
