Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/09/20 10:10:29 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.3 2001/09/19 11:54:03 mohor
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// Revision 1.3 2001/09/19 11:54:03 mohor
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// Minor changes for simulation.
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// Minor changes for simulation.
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//
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//
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// Revision 1.2 2001/09/18 14:12:43 mohor
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// Revision 1.2 2001/09/18 14:12:43 mohor
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// Trace fixed. Some registers changed, trace simplified.
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// Trace fixed. Some registers changed, trace simplified.
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Line 89... |
Line 92... |
reg BS_CHAIN_I;
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reg BS_CHAIN_I;
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wire P_TDO;
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wire P_TDO;
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wire [31:0] ADDR_RISC;
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wire [31:0] ADDR_RISC;
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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wire RISC_CS;
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wire RISC_RW;
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wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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// Connecting TAP module
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// Connecting TAP module
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dbg_top dbgTAP1(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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dbg_top dbgTAP1(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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.tdo_pad_o(P_TDO), .wb_rst_i(wb_rst_i), .mclk(Mclk),
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.tdo_pad_o(P_TDO), .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk),
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.risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
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.risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
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.risc_cs_o(RISC_CS), .risc_rw_o(RISC_RW), .wp_i(Wp), .bp_i(Bp),
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.wp_i(Wp), .bp_i(Bp),
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.opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
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.opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
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. risc_stall_o(), . risc_reset_o()
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.risc_stall_o(), .reset_o()
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);
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);
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reg TestEnabled;
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reg TestEnabled;
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Line 672... |
Line 673... |
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// print RISC registers read/write
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// print RISC registers read/write
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always @ (posedge Mclk)
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always @ (posedge Mclk)
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begin
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begin
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if(dbg_tb.dbgTAP1.risc_cs_o)
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if(dbg_tb.dbgTAP1.RISCAccess & ~dbg_tb.dbgTAP1.RISCAccess_q & dbg_tb.dbgTAP1.RW)
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if(dbg_tb.dbgTAP1.risc_rw_o)
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begin
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$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
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$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
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end
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else
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else
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begin
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if(dbg_tb.dbgTAP1.RISCAccess_q & ~dbg_tb.dbgTAP1.RISCAccess_q2 & ~dbg_tb.dbgTAP1.RW)
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$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.risc_data_i[31:0]);
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$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.risc_data_i[31:0]);
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end
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end
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end
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// print registers read/write
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// print registers read/write
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always @ (posedge Mclk)
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always @ (posedge Mclk)
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begin
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begin
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