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https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/04/22 12:54:11 mohor
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// Signal names changed to lower case.
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//
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// Revision 1.3 2001/11/26 10:47:09 mohor
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// Revision 1.3 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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//
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// Revision 1.2 2001/10/19 11:40:02 mohor
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// Revision 1.2 2001/10/19 11:40:02 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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input [WIDTH-1:0] defaulty;
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input [WIDTH-1:0] defaulty;
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output [WIDTH-1:0] data_out;
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output [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] data_out;
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//always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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always @ (posedge clk)
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//always @ (posedge clk)
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begin
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begin
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if(reset)
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if(reset)
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data_out[WIDTH-1:0]<=#1 defaulty;
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data_out[WIDTH-1:0]<=#1 defaulty;
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else
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else
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begin
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begin
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