Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
|
// CVS Revision History
|
//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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// Headers changed. All additional information is now avaliable in the README.txt file.
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Line 57... |
Line 60... |
//
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//
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|
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`include "dbg_timescale.v"
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`include "dbg_timescale.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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|
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module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Reset
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module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Reset,
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`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
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,
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ContinMode,
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ContinMode,
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TraceEnable, RecSelDepend, WpTrigger, BpTrigger, LSSTrigger,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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QualifOper, RecordPC_Wp, RecordLSEA_Wp, RecordLDATA_Wp,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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RecordSDATA_Wp, RecordReadSPR_Wp, RecordReadSPR_Bp,
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RecordSDATA, RecordReadSPR, RecordWriteSPR, RecordINSTR,
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RecordWriteSPR_Wp, RecordWriteSPR_Bp, RecordINSTR_Wp, RecordPC_Bp,
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RecordLSEA_Bp, RecordLDATA_Bp, RecordSDATA_Bp, RecordINSTR_Bp,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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LSSStopValid, IStopValid
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LSSStopValid, IStopValid,
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`endif
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`endif
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RiscStall, RiscReset
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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Line 88... |
Line 89... |
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output [31:0] DataOut;
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output [31:0] DataOut;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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|
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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output RecSelDepend;
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output ContinMode;
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output ContinMode;
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output TraceEnable;
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output TraceEnable;
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|
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output [10:0] WpTrigger;
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output [10:0] WpTrigger;
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output BpTrigger;
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output BpTrigger;
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Line 125... |
Line 125... |
output WpStopValid;
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output WpStopValid;
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output BpStopValid;
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output BpStopValid;
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output LSSStopValid;
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output LSSStopValid;
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output IStopValid;
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output IStopValid;
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|
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output [10:0] RecordPC_Wp;
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output RecordPC;
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output [10:0] RecordLSEA_Wp;
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output RecordLSEA;
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output [10:0] RecordLDATA_Wp;
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output RecordLDATA;
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output [10:0] RecordSDATA_Wp;
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output RecordSDATA;
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output [10:0] RecordReadSPR_Wp;
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output RecordReadSPR;
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output [10:0] RecordWriteSPR_Wp;
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output RecordWriteSPR;
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output [10:0] RecordINSTR_Wp;
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output RecordINSTR;
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output RecordPC_Bp;
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output RecordLSEA_Bp;
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output RecordLDATA_Bp;
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output RecordSDATA_Bp;
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output RecordReadSPR_Bp;
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output RecordWriteSPR_Bp;
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output RecordINSTR_Bp;
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`endif
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`endif
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|
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`ifdef TRACE_ENABLED
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output RiscStall;
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output RiscReset;
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wire MODER_Acc = (Address == `MODER_ADR) & Access;
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wire MODER_Acc = (Address == `MODER_ADR) & Access;
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wire RISCOP_Acc = (Address == `RISCOP_ADR) & Access;
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`ifdef TRACE_ENABLED
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wire TSEL_Acc = (Address == `TSEL_ADR) & Access;
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wire TSEL_Acc = (Address == `TSEL_ADR) & Access;
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wire QSEL_Acc = (Address == `QSEL_ADR) & Access;
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wire QSEL_Acc = (Address == `QSEL_ADR) & Access;
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wire SSEL_Acc = (Address == `SSEL_ADR) & Access;
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wire SSEL_Acc = (Address == `SSEL_ADR) & Access;
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wire RECWP0_Acc = (Address == `RECWP0_ADR) & Access;
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wire RECSEL_Acc = (Address == `RECSEL_ADR) & Access;
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wire RECWP1_Acc = (Address == `RECWP1_ADR) & Access;
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`endif
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wire RECWP2_Acc = (Address == `RECWP2_ADR) & Access;
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wire RECWP3_Acc = (Address == `RECWP3_ADR) & Access;
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wire RECWP4_Acc = (Address == `RECWP4_ADR) & Access;
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wire RECWP5_Acc = (Address == `RECWP5_ADR) & Access;
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wire RECWP6_Acc = (Address == `RECWP6_ADR) & Access;
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wire RECWP7_Acc = (Address == `RECWP7_ADR) & Access;
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wire RECWP8_Acc = (Address == `RECWP8_ADR) & Access;
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wire RECWP9_Acc = (Address == `RECWP9_ADR) & Access;
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wire RECWP10_Acc = (Address == `RECWP10_ADR) & Access;
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wire RECBP0_Acc = (Address == `RECBP0_ADR) & Access;
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wire MODER_Wr = MODER_Acc & RW;
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wire MODER_Wr = MODER_Acc & RW;
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wire RISCOP_Wr = RISCOP_Acc & RW;
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`ifdef TRACE_ENABLED
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wire TSEL_Wr = TSEL_Acc & RW;
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wire TSEL_Wr = TSEL_Acc & RW;
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wire QSEL_Wr = QSEL_Acc & RW;
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wire QSEL_Wr = QSEL_Acc & RW;
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wire SSEL_Wr = SSEL_Acc & RW;
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wire SSEL_Wr = SSEL_Acc & RW;
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wire RECWP0_Wr = RECWP0_Acc & RW;
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wire RECSEL_Wr = RECSEL_Acc & RW;
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wire RECWP1_Wr = RECWP1_Acc & RW;
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`endif
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wire RECWP2_Wr = RECWP2_Acc & RW;
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wire RECWP3_Wr = RECWP3_Acc & RW;
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wire RECWP4_Wr = RECWP4_Acc & RW;
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wire RECWP5_Wr = RECWP5_Acc & RW;
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wire RECWP6_Wr = RECWP6_Acc & RW;
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wire RECWP7_Wr = RECWP7_Acc & RW;
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wire RECWP8_Wr = RECWP8_Acc & RW;
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wire RECWP9_Wr = RECWP9_Acc & RW;
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wire RECWP10_Wr = RECWP10_Acc & RW;
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wire RECBP0_Wr = RECBP0_Acc & RW;
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|
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wire MODER_Rd = MODER_Acc & ~RW;
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wire MODER_Rd = MODER_Acc & ~RW;
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wire RISCOP_Rd = RISCOP_Acc & ~RW;
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`ifdef TRACE_ENABLED
|
wire TSEL_Rd = TSEL_Acc & ~RW;
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wire TSEL_Rd = TSEL_Acc & ~RW;
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wire QSEL_Rd = QSEL_Acc & ~RW;
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wire QSEL_Rd = QSEL_Acc & ~RW;
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wire SSEL_Rd = SSEL_Acc & ~RW;
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wire SSEL_Rd = SSEL_Acc & ~RW;
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wire RECWP0_Rd = RECWP0_Acc & ~RW;
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wire RECSEL_Rd = RECSEL_Acc & ~RW;
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wire RECWP1_Rd = RECWP1_Acc & ~RW;
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wire RECWP2_Rd = RECWP2_Acc & ~RW;
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wire RECWP3_Rd = RECWP3_Acc & ~RW;
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wire RECWP4_Rd = RECWP4_Acc & ~RW;
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wire RECWP5_Rd = RECWP5_Acc & ~RW;
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wire RECWP6_Rd = RECWP6_Acc & ~RW;
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wire RECWP7_Rd = RECWP7_Acc & ~RW;
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wire RECWP8_Rd = RECWP8_Acc & ~RW;
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wire RECWP9_Rd = RECWP9_Acc & ~RW;
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wire RECWP10_Rd = RECWP10_Acc & ~RW;
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wire RECBP0_Rd = RECBP0_Acc & ~RW;
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`endif
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`endif
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`ifdef TRACE_ENABLED
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [1:0] RISCOPOut;
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|
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`ifdef TRACE_ENABLED
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wire [31:0] TSELOut;
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wire [31:0] TSELOut;
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wire [31:0] QSELOut;
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wire [31:0] QSELOut;
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wire [31:0] SSELOut;
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wire [31:0] SSELOut;
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wire [6:0] RECSELOut;
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`endif
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wire [31:0] RECWP0Out;
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`ifdef TRACE_ENABLED
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wire [31:0] RECWP1Out;
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assign MODEROut[15:0] = 16'h0001;
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wire [31:0] RECWP2Out;
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assign MODEROut[31:18] = 14'h0;
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wire [31:0] RECWP3Out;
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`else
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wire [31:0] RECWP4Out;
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assign MODEROut[31:0] = 32'h0000;
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wire [31:0] RECWP5Out;
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wire [31:0] RECWP6Out;
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wire [31:0] RECWP7Out;
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wire [31:0] RECWP8Out;
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wire [31:0] RECWP9Out;
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wire [31:0] RECWP10Out;
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wire [31:0] RECBP0Out;
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`endif
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`endif
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dbg_register #(2) RISCOP (.DataIn(DataIn[1:0]), .DataOut(RISCOPOut[1:0]), .Write(RISCOP_Wr), .Clk(Clk), .Reset(Reset), .Default(`RISCOP_DEF));
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|
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`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
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dbg_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
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dbg_register #(2) MODER (.DataIn(DataIn[17:16]), .DataOut(MODEROut[17:16]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
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dbg_register #(32) TSEL (.DataIn(DataIn), .DataOut(TSELOut), .Write(TSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`TSEL_DEF));
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dbg_register #(32) TSEL (.DataIn(DataIn), .DataOut(TSELOut), .Write(TSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`TSEL_DEF));
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dbg_register #(32) QSEL (.DataIn(DataIn), .DataOut(QSELOut), .Write(QSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`QSEL_DEF));
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dbg_register #(32) QSEL (.DataIn(DataIn), .DataOut(QSELOut), .Write(QSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`QSEL_DEF));
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dbg_register #(32) SSEL (.DataIn(DataIn), .DataOut(SSELOut), .Write(SSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`SSEL_DEF));
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dbg_register #(32) SSEL (.DataIn(DataIn), .DataOut(SSELOut), .Write(SSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`SSEL_DEF));
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dbg_register #(7) RECSEL (.DataIn(DataIn[6:0]), .DataOut(RECSELOut), .Write(RECSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECSEL_DEF));
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dbg_register #(32) RECWP0 (.DataIn(DataIn), .DataOut(RECWP0Out), .Write(RECWP0_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP0_DEF));
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dbg_register #(32) RECWP1 (.DataIn(DataIn), .DataOut(RECWP1Out), .Write(RECWP1_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP1_DEF));
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dbg_register #(32) RECWP2 (.DataIn(DataIn), .DataOut(RECWP2Out), .Write(RECWP2_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP2_DEF));
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dbg_register #(32) RECWP3 (.DataIn(DataIn), .DataOut(RECWP3Out), .Write(RECWP3_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP3_DEF));
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dbg_register #(32) RECWP4 (.DataIn(DataIn), .DataOut(RECWP4Out), .Write(RECWP4_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP4_DEF));
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dbg_register #(32) RECWP5 (.DataIn(DataIn), .DataOut(RECWP5Out), .Write(RECWP5_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP5_DEF));
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dbg_register #(32) RECWP6 (.DataIn(DataIn), .DataOut(RECWP6Out), .Write(RECWP6_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP6_DEF));
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dbg_register #(32) RECWP7 (.DataIn(DataIn), .DataOut(RECWP7Out), .Write(RECWP7_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP7_DEF));
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dbg_register #(32) RECWP8 (.DataIn(DataIn), .DataOut(RECWP8Out), .Write(RECWP8_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP8_DEF));
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dbg_register #(32) RECWP9 (.DataIn(DataIn), .DataOut(RECWP9Out), .Write(RECWP9_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP9_DEF));
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dbg_register #(32) RECWP10(.DataIn(DataIn), .DataOut(RECWP10Out), .Write(RECWP10_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP10_DEF));
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dbg_register #(32) RECBP0 (.DataIn(DataIn), .DataOut(RECBP0Out), .Write(RECBP0_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECBP0_DEF));
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|
`endif
|
`endif
|
|
|
|
|
`ifdef TRACE_ENABLED
|
|
always @ (posedge Clk)
|
always @ (posedge Clk)
|
begin
|
begin
|
if(MODER_Rd) DataOut<= #Tp MODEROut;
|
if(MODER_Rd) DataOut<= #Tp MODEROut;
|
else
|
else
|
|
if(RISCOP_Rd) DataOut<= #Tp {30'h0, RISCOPOut};
|
|
`ifdef TRACE_ENABLED
|
|
else
|
if(TSEL_Rd) DataOut<= #Tp TSELOut;
|
if(TSEL_Rd) DataOut<= #Tp TSELOut;
|
else
|
else
|
if(QSEL_Rd) DataOut<= #Tp QSELOut;
|
if(QSEL_Rd) DataOut<= #Tp QSELOut;
|
else
|
else
|
if(SSEL_Rd) DataOut<= #Tp SSELOut;
|
if(SSEL_Rd) DataOut<= #Tp SSELOut;
|
else
|
else
|
if(RECWP0_Rd) DataOut<= #Tp RECWP0Out;
|
if(RECSEL_Rd) DataOut<= #Tp {25'h0, RECSELOut};
|
else
|
`endif
|
if(RECWP1_Rd) DataOut<= #Tp RECWP1Out;
|
|
else
|
|
if(RECWP2_Rd) DataOut<= #Tp RECWP2Out;
|
|
else
|
|
if(RECWP3_Rd) DataOut<= #Tp RECWP3Out;
|
|
else
|
|
if(RECWP4_Rd) DataOut<= #Tp RECWP4Out;
|
|
else
|
|
if(RECWP5_Rd) DataOut<= #Tp RECWP5Out;
|
|
else
|
|
if(RECWP6_Rd) DataOut<= #Tp RECWP6Out;
|
|
else
|
|
if(RECWP7_Rd) DataOut<= #Tp RECWP7Out;
|
|
else
|
|
if(RECWP8_Rd) DataOut<= #Tp RECWP8Out;
|
|
else
|
|
if(RECWP9_Rd) DataOut<= #Tp RECWP9Out;
|
|
else
|
|
if(RECWP10_Rd) DataOut<= #Tp RECWP10Out;
|
|
else
|
|
if(RECBP0_Rd) DataOut<= #Tp RECBP0Out;
|
|
else DataOut<= #Tp 'h0;
|
else DataOut<= #Tp 'h0;
|
end
|
end
|
`endif
|
|
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign ContinMode = MODEROut[0];
|
assign TraceEnable = MODEROut[16];
|
assign TraceEnable = MODEROut[1];
|
assign ContinMode = MODEROut[17];
|
assign RecSelDepend = MODEROut[2];
|
|
|
|
assign WpTrigger[10:0] = TSELOut[10:0];
|
assign WpTrigger[10:0] = TSELOut[10:0];
|
assign WpTriggerValid = TSELOut[11];
|
assign WpTriggerValid = TSELOut[11];
|
assign BpTrigger = TSELOut[12];
|
assign BpTrigger = TSELOut[12];
|
assign BpTriggerValid = TSELOut[13];
|
assign BpTriggerValid = TSELOut[13];
|
Line 313... |
Line 253... |
assign IStop[1:0] = SSELOut[22:21];
|
assign IStop[1:0] = SSELOut[22:21];
|
assign IStopValid = SSELOut[23];
|
assign IStopValid = SSELOut[23];
|
assign StopOper[1:0] = SSELOut[31:30];
|
assign StopOper[1:0] = SSELOut[31:30];
|
|
|
|
|
assign RecordPC_Wp[0] = RECWP0Out[0];
|
assign RecordPC = RECSELOut[0];
|
assign RecordLSEA_Wp[0] = RECWP0Out[1];
|
assign RecordLSEA = RECSELOut[1];
|
assign RecordLDATA_Wp[0] = RECWP0Out[2];
|
assign RecordLDATA = RECSELOut[2];
|
assign RecordSDATA_Wp[0] = RECWP0Out[3];
|
assign RecordSDATA = RECSELOut[3];
|
assign RecordReadSPR_Wp[0] = RECWP0Out[4];
|
assign RecordReadSPR = RECSELOut[4];
|
assign RecordWriteSPR_Wp[0] = RECWP0Out[5];
|
assign RecordWriteSPR = RECSELOut[5];
|
assign RecordINSTR_Wp[0] = RECWP0Out[6];
|
assign RecordINSTR = RECSELOut[6];
|
|
|
|
|
assign RecordPC_Wp[1] = RECWP1Out[0];
|
|
assign RecordLSEA_Wp[1] = RECWP1Out[1];
|
|
assign RecordLDATA_Wp[1] = RECWP1Out[2];
|
|
assign RecordSDATA_Wp[1] = RECWP1Out[3];
|
|
assign RecordReadSPR_Wp[1] = RECWP1Out[4];
|
|
assign RecordWriteSPR_Wp[1] = RECWP1Out[5];
|
|
assign RecordINSTR_Wp[1] = RECWP1Out[6];
|
|
|
|
|
|
assign RecordPC_Wp[2] = RECWP2Out[0];
|
|
assign RecordLSEA_Wp[2] = RECWP2Out[1];
|
|
assign RecordLDATA_Wp[2] = RECWP2Out[2];
|
|
assign RecordSDATA_Wp[2] = RECWP2Out[3];
|
|
assign RecordReadSPR_Wp[2] = RECWP2Out[4];
|
|
assign RecordWriteSPR_Wp[2] = RECWP2Out[5];
|
|
assign RecordINSTR_Wp[2] = RECWP2Out[6];
|
|
|
|
|
|
assign RecordPC_Wp[3] = RECWP3Out[0];
|
|
assign RecordLSEA_Wp[3] = RECWP3Out[1];
|
|
assign RecordLDATA_Wp[3] = RECWP3Out[2];
|
|
assign RecordSDATA_Wp[3] = RECWP3Out[3];
|
|
assign RecordReadSPR_Wp[3] = RECWP3Out[4];
|
|
assign RecordWriteSPR_Wp[3] = RECWP3Out[5];
|
|
assign RecordINSTR_Wp[3] = RECWP3Out[6];
|
|
|
|
|
|
assign RecordPC_Wp[4] = RECWP4Out[0];
|
|
assign RecordLSEA_Wp[4] = RECWP4Out[1];
|
|
assign RecordLDATA_Wp[4] = RECWP4Out[2];
|
|
assign RecordSDATA_Wp[4] = RECWP4Out[3];
|
|
assign RecordReadSPR_Wp[4] = RECWP4Out[4];
|
|
assign RecordWriteSPR_Wp[4] = RECWP4Out[5];
|
|
assign RecordINSTR_Wp[4] = RECWP4Out[6];
|
|
|
|
|
|
assign RecordPC_Wp[5] = RECWP5Out[0];
|
|
assign RecordLSEA_Wp[5] = RECWP5Out[1];
|
|
assign RecordLDATA_Wp[5] = RECWP5Out[2];
|
|
assign RecordSDATA_Wp[5] = RECWP5Out[3];
|
|
assign RecordReadSPR_Wp[5] = RECWP5Out[4];
|
|
assign RecordWriteSPR_Wp[5] = RECWP5Out[5];
|
|
assign RecordINSTR_Wp[5] = RECWP5Out[6];
|
|
|
|
|
|
assign RecordPC_Wp[6] = RECWP6Out[0];
|
|
assign RecordLSEA_Wp[6] = RECWP6Out[1];
|
|
assign RecordLDATA_Wp[6] = RECWP6Out[2];
|
|
assign RecordSDATA_Wp[6] = RECWP6Out[3];
|
|
assign RecordReadSPR_Wp[6] = RECWP6Out[4];
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assign RecordWriteSPR_Wp[6] = RECWP6Out[5];
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assign RecordINSTR_Wp[6] = RECWP6Out[6];
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assign RecordPC_Wp[7] = RECWP7Out[0];
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assign RecordLSEA_Wp[7] = RECWP7Out[1];
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assign RecordLDATA_Wp[7] = RECWP7Out[2];
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assign RecordSDATA_Wp[7] = RECWP7Out[3];
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assign RecordReadSPR_Wp[7] = RECWP7Out[4];
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assign RecordWriteSPR_Wp[7] = RECWP7Out[5];
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assign RecordINSTR_Wp[7] = RECWP7Out[6];
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assign RecordPC_Wp[8] = RECWP8Out[0];
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assign RecordLSEA_Wp[8] = RECWP8Out[1];
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assign RecordLDATA_Wp[8] = RECWP8Out[2];
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assign RecordSDATA_Wp[8] = RECWP8Out[3];
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assign RecordReadSPR_Wp[8] = RECWP8Out[4];
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assign RecordWriteSPR_Wp[8] = RECWP8Out[5];
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assign RecordINSTR_Wp[8] = RECWP8Out[6];
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assign RecordPC_Wp[9] = RECWP9Out[0];
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assign RecordLSEA_Wp[9] = RECWP9Out[1];
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assign RecordLDATA_Wp[9] = RECWP9Out[2];
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assign RecordSDATA_Wp[9] = RECWP9Out[3];
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assign RecordReadSPR_Wp[9] = RECWP9Out[4];
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assign RecordWriteSPR_Wp[9] = RECWP9Out[5];
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assign RecordINSTR_Wp[9] = RECWP9Out[6];
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assign RecordPC_Wp[10] = RECWP10Out[0];
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assign RecordLSEA_Wp[10] = RECWP10Out[1];
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assign RecordLDATA_Wp[10] = RECWP10Out[2];
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assign RecordSDATA_Wp[10] = RECWP10Out[3];
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assign RecordReadSPR_Wp[10] = RECWP10Out[4];
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assign RecordWriteSPR_Wp[10] = RECWP10Out[5];
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assign RecordINSTR_Wp[10] = RECWP10Out[6];
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assign RecordPC_Bp = RECBP0Out[0];
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assign RecordLSEA_Bp = RECBP0Out[1];
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assign RecordLDATA_Bp = RECBP0Out[2];
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assign RecordSDATA_Bp = RECBP0Out[3];
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assign RecordReadSPR_Bp = RECBP0Out[4];
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assign RecordWriteSPR_Bp = RECBP0Out[5];
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assign RecordINSTR_Bp = RECBP0Out[6];
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`endif
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`endif
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assign RiscStall = RISCOPOut[0];
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assign RiscReset = RISCOPOut[1];
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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