URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_7/] [sim/] [rtl_sim/] [run/] [do.do] - Diff between revs 2 and 5

Rev 2	Rev 5
Line 5...	Line 5...
`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v}`	`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v}`
`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_timescale.v}`	`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_timescale.v}`
`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v}`	`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v}`
`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v}`	`vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v}`

	`vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb_defines.v}`
`vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb.v}`	`vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb.v}`


`vsim work.dbg_tb`	`vsim work.dbg_tb`