| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/19 11:54:03 mohor
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// Minor changes for simulation.
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//
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// Revision 1.2 2001/09/18 14:12:43 mohor
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// Revision 1.2 2001/09/18 14:12:43 mohor
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// Trace fixed. Some registers changed, trace simplified.
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// Trace fixed. Some registers changed, trace simplified.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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| Line 74... |
Line 77... |
parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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reg P_TMS, P_TCK;
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reg P_TMS, P_TCK;
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reg P_TRST, P_TDI;
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reg P_TRST, P_TDI;
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reg P_PowerONReset;
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reg wb_rst_i;
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reg Mclk;
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reg Mclk;
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reg [10:0] Wp;
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reg [10:0] Wp;
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reg Bp;
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reg Bp;
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reg [3:0] LsStatus;
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reg [3:0] LsStatus;
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| Line 88... |
Line 91... |
wire P_TDO;
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wire P_TDO;
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wire [31:0] ADDR_RISC;
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wire [31:0] ADDR_RISC;
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
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wire RISC_CS;
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wire RISC_CS;
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wire RISC_RW;
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wire RISC_RW;
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wire RISC_STALL_O;
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wire RISC_RESET_O;
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wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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wire [`OPSELECTWIDTH-1:0] OpSelect;
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// Connecting TAP module
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// Connecting TAP module
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dbg_top dbgTAP1(.P_TMS(P_TMS), .P_TCK(P_TCK), .P_TRST(P_TRST), .P_TDI(P_TDI),
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dbg_top dbgTAP1(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
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.P_TDO(P_TDO), .P_PowerONReset(P_PowerONReset), .Mclk(Mclk),
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.tdo_pad_o(P_TDO), .wb_rst_i(wb_rst_i), .mclk(Mclk),
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.RISC_ADDR(ADDR_RISC), .RISC_DATA_IN(DATAOUT_RISC), .RISC_DATA_OUT(DATAIN_RISC),
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.risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
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.RISC_CS(RISC_CS), .RISC_RW(RISC_RW), .Wp(Wp), .Bp(Bp),
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.risc_cs_o(RISC_CS), .risc_rw_o(RISC_RW), .wp_i(Wp), .bp_i(Bp),
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.OpSelect(OpSelect), .LsStatus(LsStatus), .IStatus(IStatus),
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.opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
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.RISC_STALL_O(RISC_STALL_O), .RISC_RESET_O(RISC_RESET_O), .BS_CHAIN_I(BS_CHAIN_I)
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. risc_stall_o(), . risc_reset_o()
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);
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);
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reg TestEnabled;
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reg TestEnabled;
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//integer i;
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initial
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initial
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begin
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begin
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TestEnabled<=#Tp 0;
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TestEnabled<=#Tp 0;
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P_TMS<=#Tp 0;
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P_TMS<=#Tp 0;
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P_TCK<=#Tp 0;
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P_TCK<=#Tp 0;
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P_TDI<=#Tp 0;
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P_TDI<=#Tp 0;
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P_TRST<=#Tp 1;
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Wp<=#Tp 0;
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Wp<=#Tp 0;
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Bp<=#Tp 0;
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Bp<=#Tp 0;
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LsStatus<=#Tp 0;
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LsStatus<=#Tp 0;
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IStatus<=#Tp 0;
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IStatus<=#Tp 0;
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P_PowerONReset<=#Tp 1;
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wb_rst_i<=#Tp 0;
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#100 P_PowerONReset<=#Tp 0; // PowerONReset is active low
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P_TRST<=#Tp 1;
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#100 P_PowerONReset<=#Tp 1;
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#100 wb_rst_i<=#Tp 1;
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P_TRST<=#Tp 0;
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#100 wb_rst_i<=#Tp 0;
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P_TRST<=#Tp 1;
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#Tp TestEnabled<=#Tp 1;
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#Tp TestEnabled<=#Tp 1;
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end
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end
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// Generating master clock (RISC clock) 200 MHz
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// Generating master clock (RISC clock) 200 MHz
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| Line 140... |
Line 142... |
end
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end
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// Generating random number for use in DATAOUT_RISC[31:0]
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// Generating random number for use in DATAOUT_RISC[31:0]
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reg [31:0] RandNumb;
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reg [31:0] RandNumb;
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always @ (posedge Mclk or negedge P_PowerONReset) // PowerONReset is active low
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always @ (posedge Mclk or posedge wb_rst_i)
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begin
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begin
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if(~P_PowerONReset)
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if(wb_rst_i)
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RandNumb[31:0]<=#Tp 0;
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RandNumb[31:0]<=#Tp 0;
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else
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else
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RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
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RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
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end
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end
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| Line 177... |
Line 179... |
SetInstruction(`CHAIN_SELECT);
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SetInstruction(`CHAIN_SELECT);
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ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
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ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
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SetInstruction(`DEBUG);
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SetInstruction(`DEBUG);
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/*
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//
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// Testing internal registers
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// Testing internal registers
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
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WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
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WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
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WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
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WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
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WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
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WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
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WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
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WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
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WriteRegister(32'h0000dead, `RECSEL_ADR, 8'hfb); // {data, addr, crc}
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(`RECSEL_ADR, 8'hc4); // {addr, crc}
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
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*/
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//
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// testing trigger and qualifier
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// testing trigger and qualifier
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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| Line 220... |
Line 222... |
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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// End: Anything starts trigger and qualifier //
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// End: Anything starts trigger and qualifier //
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/* Anything starts trigger, breakpoint starts qualifier
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/* Anything starts trigger, breakpoint starts qualifier
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// Uncomment this part when you want to test it.
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#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
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#1000 WriteRegister(`QUALIFOP_OR | `BPQUALIFVALID | `BPQUALIF, `QSEL_ADR, 8'had); // Any qualifier
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#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
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#1000 WriteRegister(32'h00000000, `TSEL_ADR, 8'h06); // Any trigger
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#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
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#1000 WriteRegister(32'h0000000c, `RECSEL_ADR, 8'h0f); // Two samples are selected for recording (RECSDATA and RECLDATA)
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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| Line 235... |
Line 238... |
#1 Bp = 0; // Clear breakpoint
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#1 Bp = 0; // Clear breakpoint
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// End: Anything starts trigger, breakpoint starts qualifier */
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// End: Anything starts trigger, breakpoint starts qualifier */
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/* Anything starts qualifier, breakpoint starts trigger
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/* Anything starts qualifier, breakpoint starts trigger
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// Uncomment this part when you want to test it.
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#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
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#1000 WriteRegister(32'h00000000, `QSEL_ADR, 8'h50); // Any qualifier
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#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
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#1000 WriteRegister(`LSSTRIG_0 | `LSSTRIG_2 | `LSSTRIGVALID | `WPTRIG_4 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'had); // Trigger is AND of Watchpoint4 and LSSTRIG[0] and LSSTRIG[2]
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#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
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#1000 WriteRegister(32'h00000003, `RECSEL_ADR, 8'h0c); // Two samples are selected for recording (RECPC and RECLSEA)
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(32'h00000000, `SSEL_ADR, 8'h34); // No stop signal
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hd4); // Trace enabled
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| Line 254... |
Line 258... |
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// Reading data from the trace buffer
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SetInstruction(`CHAIN_SELECT);
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SetInstruction(`CHAIN_SELECT);
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ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
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ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
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SetInstruction(`DEBUG);
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SetInstruction(`DEBUG);
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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| Line 270... |
Line 275... |
ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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ReadTraceBuffer;
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// for(i=0;i<1500;i=i+1)
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// ReadTraceBuffer;
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`endif // TRACE_ENABLED
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`endif // TRACE_ENABLED
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| Line 602... |
Line 605... |
GenClk(1);
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GenClk(1);
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P_TMS<=#Tp 0;
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P_TMS<=#Tp 0;
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GenClk(1); // we are in RunTestIdle
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GenClk(1); // we are in RunTestIdle
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GenClk(5); // Igor !!!! To mora iti ven. Tu je le zato, da se tisti write-i naredijo
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GenClk(5); // Extra clocks needed for operations to finish
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end
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end
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endtask
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endtask
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| Line 669... |
Line 672... |
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// print RISC registers read/write
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// print RISC registers read/write
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always @ (posedge Mclk)
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always @ (posedge Mclk)
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begin
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begin
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if(dbg_tb.dbgTAP1.RISC_CS)
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if(dbg_tb.dbgTAP1.risc_cs_o)
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if(dbg_tb.dbgTAP1.RISC_RW)
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if(dbg_tb.dbgTAP1.risc_rw_o)
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begin
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begin
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$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
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$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
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end
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end
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else
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else
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begin
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begin
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$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.RISC_DATA_IN[31:0]);
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$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.risc_data_i[31:0]);
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end
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end
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end
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end
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// print registers read/write
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// print registers read/write
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| Line 689... |
Line 692... |
if(dbg_tb.dbgTAP1.RegAccess_q & ~dbg_tb.dbgTAP1.RegAccess_q2)
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if(dbg_tb.dbgTAP1.RegAccess_q & ~dbg_tb.dbgTAP1.RegAccess_q2)
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begin
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begin
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if(dbg_tb.dbgTAP1.RW)
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if(dbg_tb.dbgTAP1.RW)
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$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.DataOut[31:0]);
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$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.DataOut[31:0]);
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else
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else
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$write("\n\t\tRead from Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.RegDataIn[31:0]);
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$write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.RegDataIn[31:0]);
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end
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end
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end
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end
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// print CRC error
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// print CRC error
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