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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.2 2001/06/01 22:22:35 mohor
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// Revision 1.2 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.1 2001/05/18 13:12:09 mohor
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// Revision 1.1 2001/05/18 13:12:09 mohor
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// Header changed. All additional information is now avaliable in this README.txt file.
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// Header changed. All additional information is now avaliable in this README.txt file.
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http://www.opencores.org/cores/DebugInterface/
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http://www.opencores.org/cores/DebugInterface/
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Documentation can also be found there. For direct download of the
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Documentation can also be found there. For direct download of the
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documentation go to:
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documentation go to:
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http://www.opencores.org/cgi-bin/cvsget.cgi/DebugInterface/Doc/DbgSupp.pdf
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http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf
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OVERVIEW (main Features):
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OVERVIEW (main Features):
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debugger or BS tester connects to the core via JTAG port.
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debugger or BS tester connects to the core via JTAG port.
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The Development Port also contains a trace and support for
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The Development Port also contains a trace and support for
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tracing the program flow, execution coverage and profiling
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tracing the program flow, execution coverage and profiling
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the code.
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the code.
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dbg_tb.v is a testbench file.
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file_communication.v is used for simulating the whole design together with the
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debugger through two files that make a JTAG interface
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dbg_top.v is top level module of the development interface design
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COMPATIBILITY:
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COMPATIBILITY:
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- WISHBONE rev B.1
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- WISHBONE rev B.1
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Mclk clock signal. Simulation should do the same.
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Mclk clock signal. Simulation should do the same.
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TO DO:
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TO DO:
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- Add reset and cpu stall signals that are related to the RISCOP register
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- Add a WISHBONE master support if needed
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- Add a WISHBONE master support
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- Add support for boundary scan (This is already done, but not yet incorporated in the design)
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- Add support for boundary scan (This is already done, but not yet incorporated in the design)
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- Signal RecSelDepend is not connected anywhere, yet. Read the pdf for details on that.
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No newline at end of file
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No newline at end of file
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