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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_crc8_d1.v] - Diff between revs 20 and 26

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Rev 20	Rev 26
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2001/11/26 10:47:09 mohor`
	`// Crc generation is different for read or write commands. Small synthesys fixes.`
	`//`
`// Revision 1.3 2001/10/19 11:40:02 mohor`	`// Revision 1.3 2001/10/19 11:40:02 mohor`
`// dbg_timescale.v changed to timescale.v This is done for the simulation of`	`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
`// few different cores in a single project.`	`// few different cores in a single project.`
`//`	`//`
`// Revision 1.2 2001/09/20 10:11:25 mohor`	`// Revision 1.2 2001/09/20 10:11:25 mohor`
Line 106...	Line 109...


`output [7:0] CrcOut;`	`output [7:0] CrcOut;`
`reg [7:0] CrcOut;`	`reg [7:0] CrcOut;`


`always @ (posedge Clk or posedge Reset)`
`begin`
`if(Reset)`
`CrcOut[7:0] <= #Tp 0;`
`else`
`if(SyncResetCrc)`
`CrcOut[7:0] <= #Tp 0;`
`else`
`if(EnableCrc)`
`CrcOut[7:0] <= #Tp nextCRC8_D1(Data, CrcOut);`
`end`


`// polynomial: (0 1 2 8)`	`// polynomial: (0 1 2 8)`
`// data width: 1`	`// data width: 1`
`function [7:0] nextCRC8_D1;`	`function [7:0] nextCRC8_D1;`

`input Data;`	`input Data;`
Line 148...	Line 137...

`nextCRC8_D1 = NewCRC;`	`nextCRC8_D1 = NewCRC;`
`end`	`end`
`endfunction`	`endfunction`


	`always @ (posedge Clk or posedge Reset)`
	`begin`
	`if(Reset)`
	`CrcOut[7:0] <= #Tp 0;`
	`else`
	`if(SyncResetCrc)`
	`CrcOut[7:0] <= #Tp 0;`
	`else`
	`if(EnableCrc)`
	`CrcOut[7:0] <= #Tp nextCRC8_D1(Data, CrcOut);`
	`end`



`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_crc8_d1.v] - Diff between revs 20 and 26