| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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// Headers changed. All additional information is now avaliable in the README.txt file.
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Line 60... |
//
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//
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// Enable TRACE
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// Enable TRACE
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//`define TRACE_ENABLED // Uncomment this define to activate the trace
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`define TRACE_ENABLED // Uncomment this define to activate the trace
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// Define IDCODE Value
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// Define IDCODE Value
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`define IDCODE_VALUE 32'hdeadbeef
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`define IDCODE_VALUE 32'hdeadbeef
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// Define master clock (RISC clock)
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// Define master clock (RISC clock)
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`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
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`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
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// Length of the Instruction register
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// Length of the Instruction register
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`define IR_LENGTH 4
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`define IR_LENGTH 4
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// Length of the Data register (must be equal to the longest scan chain)
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// Length of the Data register (must be equal to the longest scan chain)
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Line 83... |
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// Length of the CRC
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// Length of the CRC
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`define CRC_LENGTH 8
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`define CRC_LENGTH 8
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// Trace buffer size and counter and write/read pointer width
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// Trace buffer size and counter and write/read pointer width
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`define TRACECOUNTERWIDTH 10
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`define TRACECOUNTERWIDTH 5 //10
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`define TRACEBUFFERLENGTH 1024 //2^10
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`define TRACEBUFFERLENGTH 32 // 2^5 1024 //2^10
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`define TRACESAMPLEWIDTH 36
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`define TRACESAMPLEWIDTH 36
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// OpSelect width
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// OpSelect width
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`define OPSELECTWIDTH 3
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`define OPSELECTWIDTH 3
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`define OPSELECTIONCOUNTER 8 //2^3
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`define OPSELECTIONCOUNTER 8 //2^3
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Line 116... |
// Registers addresses
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// Registers addresses
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`define MODER_ADR 5'h00
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`define MODER_ADR 5'h00
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`define TSEL_ADR 5'h01
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`define TSEL_ADR 5'h01
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`define QSEL_ADR 5'h02
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`define QSEL_ADR 5'h02
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`define SSEL_ADR 5'h03
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`define SSEL_ADR 5'h03
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`define RISCOP_ADR 5'h04
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`define RECWP0_ADR 5'h10
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`define RECSEL_ADR 5'h10
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`define RECWP1_ADR 5'h11
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`define RECWP2_ADR 5'h12
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`define RECWP3_ADR 5'h13
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`define RECWP4_ADR 5'h14
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`define RECWP5_ADR 5'h15
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`define RECWP6_ADR 5'h16
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`define RECWP7_ADR 5'h17
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`define RECWP8_ADR 5'h18
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`define RECWP9_ADR 5'h19
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`define RECWP10_ADR 5'h1A
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`define RECBP0_ADR 5'h1B
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// Registers default values (after reset)
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// Registers default values (after reset)
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`define MODER_DEF 32'h00000000
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`define MODER_DEF 2'h0
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`define TSEL_DEF 32'h00000000
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`define TSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define QSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define SSEL_DEF 32'h00000000
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`define RISCOP_DEF 2'h0
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`define RECWP0_DEF 32'h00000000
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`define RECSEL_DEF 7'h00
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`define RECWP1_DEF 32'h00000000
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`define RECWP2_DEF 32'h00000000
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`define RECWP3_DEF 32'h00000000
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`define RECWP4_DEF 32'h00000000
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`define RECWP5_DEF 32'h00000000
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`define RECWP6_DEF 32'h00000000
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`define RECWP7_DEF 32'h00000000
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`define RECWP8_DEF 32'h00000000
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`define RECWP9_DEF 32'h00000000
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`define RECWP10_DEF 32'h00000000
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`define RECBP0_DEF 32'h00000000
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