OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Diff between revs 5 and 9

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 5 Rev 9
Line 43... Line 43...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.2  2001/09/18 14:13:47  mohor
 
// Trace fixed. Some registers changed, trace simplified.
 
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
// Initial official release.
//
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
// This is a backup. It is not a fully working version. Not for use, yet.
Line 82... Line 85...
`define CHAIN_ID_LENGTH 4
`define CHAIN_ID_LENGTH 4
 
 
// Length of the CRC
// Length of the CRC
`define CRC_LENGTH      8
`define CRC_LENGTH      8
 
 
// Trace buffer size and counter and write/read pointer width
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH        5 //10
`define TRACECOUNTERWIDTH        5
`define TRACEBUFFERLENGTH        32 // 2^5 1024 //2^10
`define TRACEBUFFERLENGTH        32 // 2^5
 
 
`define TRACESAMPLEWIDTH         36
`define TRACESAMPLEWIDTH         36
 
 
// OpSelect width
// OpSelect width
`define OPSELECTWIDTH            3
`define OPSELECTWIDTH            3
`define OPSELECTIONCOUNTER       8    //2^3
`define OPSELECTIONCOUNTER       8    //2^3
 
 
// Supported Instructions
// Supported Instructions
`define EXTEST          4'b0000
`define EXTEST          5'b00000
`define SAMPLE_PRELOAD  4'b0001
`define SAMPLE_PRELOAD  5'b00001
`define IDCODE          4'b0010
`define IDCODE          5'b00010
`define CHAIN_SELECT    4'b0011
`define CHAIN_SELECT    5'b00011
`define INTEST          4'b0100
`define INTEST          5'b00100
`define CLAMP           4'b0101
`define CLAMP           5'b00101
`define CLAMPZ          4'b0110
`define CLAMPZ          5'b00110
`define HIGHZ           4'b0111
`define HIGHZ           5'b00111
`define DEBUG           4'b1000
`define DEBUG           5'b01000
`define BYPASS          4'b1111
`define BYPASS          5'b01111
 
 
// Chains
// Chains
`define GLOBAL_BS_CHAIN     4'b0000
`define GLOBAL_BS_CHAIN     4'b0000
`define RISC_DEBUG_CHAIN    4'b0001
`define RISC_DEBUG_CHAIN    4'b0001
`define RISC_TEST_CHAIN     4'b0010
`define RISC_TEST_CHAIN     4'b0010
Line 126... Line 130...
`define MODER_DEF           2'h0
`define MODER_DEF           2'h0
`define TSEL_DEF            32'h00000000
`define TSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define RISCOP_DEF          2'h0
`define RISCOP_DEF          2'h0
`define RECSEL_DEF          7'h00
`define RECSEL_DEF          7'h0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.