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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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// Revision 1.2 2001/10/19 11:40:02 mohor
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// Revision 1.2 2001/10/19 11:40:02 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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// few different cores in a single project.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default);
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module dbg_register(data_in, data_out, write, clk, reset, defaulty);
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parameter WIDTH = 8; // default parameter of the register width
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parameter WIDTH = 8; // default parameter of the register width
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input [WIDTH-1:0] DataIn;
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input [WIDTH-1:0] data_in;
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input Write;
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input write;
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input Clk;
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input clk;
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input Reset;
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input reset;
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input [WIDTH-1:0] Default;
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input [WIDTH-1:0] defaulty;
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output [WIDTH-1:0] DataOut;
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output [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] DataOut;
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reg [WIDTH-1:0] data_out;
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//always @ (posedge Clk or posedge Reset)
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//always @ (posedge clk or posedge reset)
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always @ (posedge Clk)
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always @ (posedge clk)
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begin
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begin
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if(Reset)
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if(reset)
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DataOut[WIDTH-1:0]<=#1 Default;
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data_out[WIDTH-1:0]<=#1 defaulty;
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else
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else
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begin
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begin
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if(Write) // write
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if(write) // write
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DataOut[WIDTH-1:0]<=#1 DataIn[WIDTH-1:0];
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data_out[WIDTH-1:0]<=#1 data_in[WIDTH-1:0];
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end
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end
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end
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end
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endmodule // Register
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endmodule // Register
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