URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_register.v] - Diff between revs 44 and 46

Rev 44	Rev 46
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2002/04/22 12:54:11 mohor`
	`// Signal names changed to lower case.`
	`//`
`// Revision 1.3 2001/11/26 10:47:09 mohor`	`// Revision 1.3 2001/11/26 10:47:09 mohor`
`// Crc generation is different for read or write commands. Small synthesys fixes.`	`// Crc generation is different for read or write commands. Small synthesys fixes.`
`//`	`//`
`// Revision 1.2 2001/10/19 11:40:02 mohor`	`// Revision 1.2 2001/10/19 11:40:02 mohor`
`// dbg_timescale.v changed to timescale.v This is done for the simulation of`	`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
Line 76...	Line 79...
`input [WIDTH-1:0] defaulty;`	`input [WIDTH-1:0] defaulty;`

`output [WIDTH-1:0] data_out;`	`output [WIDTH-1:0] data_out;`
`reg [WIDTH-1:0] data_out;`	`reg [WIDTH-1:0] data_out;`

`//always @ (posedge clk or posedge reset)`	`always @ (posedge clk or posedge reset)`
`always @ (posedge clk)`	`//always @ (posedge clk)`
`begin`	`begin`
`if(reset)`	`if(reset)`
`data_out[WIDTH-1:0]<=#1 defaulty;`	`data_out[WIDTH-1:0]<=#1 defaulty;`
`else`	`else`
`begin`	`begin`