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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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//
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`include "dbg_timescale.v"
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`include "dbg_timescale.v"
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Reset,
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module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset,
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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ContinMode,
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ContinMode,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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input [4:0] Address;
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input [4:0] Address;
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input RW;
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input RW;
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input Access;
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input Access;
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input Clk;
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input Clk;
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input Bp;
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input Reset;
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input Reset;
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output [31:0] DataOut;
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output [31:0] DataOut;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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`endif
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`endif
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output RiscStall;
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output RiscStall;
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output RiscReset;
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output RiscReset;
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wire MODER_Acc = (Address == `MODER_ADR) & Access;
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wire MODER_Acc = (Address == `MODER_ADR) & Access;
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wire RISCOP_Acc = (Address == `RISCOP_ADR) & Access;
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wire RISCOP_Acc = (Address == `RISCOP_ADR) & Access;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Acc = (Address == `TSEL_ADR) & Access;
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wire TSEL_Acc = (Address == `TSEL_ADR) & Access;
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wire QSEL_Acc = (Address == `QSEL_ADR) & Access;
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wire QSEL_Acc = (Address == `QSEL_ADR) & Access;
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wire RECSEL_Rd = RECSEL_Acc & ~RW;
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wire RECSEL_Rd = RECSEL_Acc & ~RW;
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`endif
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`endif
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [1:0] RISCOPOut;
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wire [1:1] RISCOPOut;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire [31:0] TSELOut;
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wire [31:0] TSELOut;
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wire [31:0] QSELOut;
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wire [31:0] QSELOut;
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wire [31:0] SSELOut;
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wire [31:0] SSELOut;
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`else
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`else
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assign MODEROut[31:0] = 32'h0000;
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assign MODEROut[31:0] = 32'h0000;
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`endif
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`endif
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dbg_register #(2) RISCOP (.DataIn(DataIn[1:0]), .DataOut(RISCOPOut[1:0]), .Write(RISCOP_Wr), .Clk(Clk), .Reset(Reset), .Default(`RISCOP_DEF));
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reg RiscStallBp;
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always @(posedge Clk or posedge Reset)
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begin
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if(Reset)
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RiscStallBp <= 1'b0;
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else
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if(Bp) // Breakpoint sets bit
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RiscStallBp <= 1'b1;
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else
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if(RISCOP_Wr) // Register access can set or clear bit
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RiscStallBp <= DataIn[0];
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end
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dbg_register #(1) RISCOP (.DataIn(DataIn[1]), .DataOut(RISCOPOut[1]), .Write(RISCOP_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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dbg_register #(2) MODER (.DataIn(DataIn[17:16]), .DataOut(MODEROut[17:16]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
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dbg_register #(2) MODER (.DataIn(DataIn[17:16]), .DataOut(MODEROut[17:16]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
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dbg_register #(32) TSEL (.DataIn(DataIn), .DataOut(TSELOut), .Write(TSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`TSEL_DEF));
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dbg_register #(32) TSEL (.DataIn(DataIn), .DataOut(TSELOut), .Write(TSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`TSEL_DEF));
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dbg_register #(32) QSEL (.DataIn(DataIn), .DataOut(QSELOut), .Write(QSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`QSEL_DEF));
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dbg_register #(32) QSEL (.DataIn(DataIn), .DataOut(QSELOut), .Write(QSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`QSEL_DEF));
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always @ (posedge Clk)
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always @ (posedge Clk)
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begin
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begin
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if(MODER_Rd) DataOut<= #Tp MODEROut;
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if(MODER_Rd) DataOut<= #Tp MODEROut;
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else
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else
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if(RISCOP_Rd) DataOut<= #Tp {30'h0, RISCOPOut};
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if(RISCOP_Rd) DataOut<= #Tp {30'h0, RISCOPOut[1], RiscStall};
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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else
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else
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if(TSEL_Rd) DataOut<= #Tp TSELOut;
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if(TSEL_Rd) DataOut<= #Tp TSELOut;
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else
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else
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if(QSEL_Rd) DataOut<= #Tp QSELOut;
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if(QSEL_Rd) DataOut<= #Tp QSELOut;
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assign RecordReadSPR = RECSELOut[4];
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assign RecordReadSPR = RECSELOut[4];
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assign RecordWriteSPR = RECSELOut[5];
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assign RecordWriteSPR = RECSELOut[5];
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assign RecordINSTR = RECSELOut[6];
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assign RecordINSTR = RECSELOut[6];
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`endif
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`endif
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assign RiscStall = RISCOPOut[0];
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assign RiscStall = Bp | RiscStallBp; // Bp asynchronously sets the RiscStall, then RiscStallBp (from register) holds it active
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assign RiscReset = RISCOPOut[1];
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assign RiscReset = RISCOPOut[1];
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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