URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_registers.v] - Diff between revs 12 and 17

Rev 12	Rev 17
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/10/15 09:55:47 mohor`
	`// Wishbone interface added, few fixes for better performance,`
	`// hooks for boundary scan testing added.`
	`//`
`// Revision 1.2 2001/09/18 14:13:47 mohor`	`// Revision 1.2 2001/09/18 14:13:47 mohor`
`// Trace fixed. Some registers changed, trace simplified.`	`// Trace fixed. Some registers changed, trace simplified.`
`//`	`//`
`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
`// Initial official release.`	`// Initial official release.`
Line 60...	Line 64...
`// Revision 1.1.1.1 2001/05/18 06:35:10 mohor`	`// Revision 1.1.1.1 2001/05/18 06:35:10 mohor`
`// Initial release`	`// Initial release`
`//`	`//`
`//`	`//`

`include "dbg_timescale.v"	`include "timescale.v"
`include "dbg_defines.v"	`include "dbg_defines.v"

`module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset,`	`module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset,`
`ifdef TRACE_ENABLED	`ifdef TRACE_ENABLED
`ContinMode,`	`ContinMode,`