URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_registers.v] - Diff between revs 17 and 20

Rev 17	Rev 20
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2001/10/19 11:40:02 mohor`
	`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
	`// few different cores in a single project.`
	`//`
`// Revision 1.3 2001/10/15 09:55:47 mohor`	`// Revision 1.3 2001/10/15 09:55:47 mohor`
`// Wishbone interface added, few fixes for better performance,`	`// Wishbone interface added, few fixes for better performance,`
`// hooks for boundary scan testing added.`	`// hooks for boundary scan testing added.`
`//`	`//`
`// Revision 1.2 2001/09/18 14:13:47 mohor`	`// Revision 1.2 2001/09/18 14:13:47 mohor`
Line 64...	Line 68...
`// Revision 1.1.1.1 2001/05/18 06:35:10 mohor`	`// Revision 1.1.1.1 2001/05/18 06:35:10 mohor`
`// Initial release`	`// Initial release`
`//`	`//`
`//`	`//`

	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`
`include "dbg_defines.v"	`include "dbg_defines.v"

`module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset,`	`module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset,`
`ifdef TRACE_ENABLED	`ifdef TRACE_ENABLED
`ContinMode,`	`ContinMode,`