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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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// Revision 1.4 2001/10/19 11:40:02 mohor
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// Revision 1.4 2001/10/19 11:40:02 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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// few different cores in a single project.
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//
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//
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// Revision 1.3 2001/10/15 09:55:47 mohor
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// Revision 1.3 2001/10/15 09:55:47 mohor
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset,
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module dbg_registers(data_in, data_out, address, rw, access, clk, bp, reset,
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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ContinMode,
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ContinMode,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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QualifOper, RecordPC, RecordLSEA, RecordLDATA,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
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LSSStopValid, IStopValid,
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LSSStopValid, IStopValid,
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`endif
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`endif
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RiscStall, RiscReset
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risc_stall, risc_reset
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] data_in;
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input [4:0] Address;
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input [4:0] address;
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input RW;
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input rw;
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input Access;
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input access;
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input Clk;
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input clk;
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input Bp;
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input bp;
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input Reset;
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input reset;
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output [31:0] DataOut;
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output [31:0] data_out;
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reg [31:0] DataOut;
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reg [31:0] data_out;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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output ContinMode;
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output ContinMode;
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output TraceEnable;
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output TraceEnable;
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output RecordReadSPR;
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output RecordReadSPR;
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output RecordWriteSPR;
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output RecordWriteSPR;
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output RecordINSTR;
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output RecordINSTR;
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`endif
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`endif
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output RiscStall;
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output risc_stall;
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output RiscReset;
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output risc_reset;
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wire MODER_Acc = (Address == `MODER_ADR) & Access;
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wire MODER_Acc = (address == `MODER_ADR) & access;
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wire RISCOP_Acc = (Address == `RISCOP_ADR) & Access;
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wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Acc = (Address == `TSEL_ADR) & Access;
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wire TSEL_Acc = (address == `TSEL_ADR) & access;
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wire QSEL_Acc = (Address == `QSEL_ADR) & Access;
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wire QSEL_Acc = (address == `QSEL_ADR) & access;
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wire SSEL_Acc = (Address == `SSEL_ADR) & Access;
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wire SSEL_Acc = (address == `SSEL_ADR) & access;
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wire RECSEL_Acc = (Address == `RECSEL_ADR) & Access;
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wire RECSEL_Acc = (address == `RECSEL_ADR) & access;
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`endif
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`endif
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wire MODER_Wr = MODER_Acc & RW;
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wire MODER_Wr = MODER_Acc & rw;
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wire RISCOP_Wr = RISCOP_Acc & RW;
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wire RISCOP_Wr = RISCOP_Acc & rw;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Wr = TSEL_Acc & RW;
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wire TSEL_Wr = TSEL_Acc & rw;
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wire QSEL_Wr = QSEL_Acc & RW;
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wire QSEL_Wr = QSEL_Acc & rw;
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wire SSEL_Wr = SSEL_Acc & RW;
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wire SSEL_Wr = SSEL_Acc & rw;
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wire RECSEL_Wr = RECSEL_Acc & RW;
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wire RECSEL_Wr = RECSEL_Acc & rw;
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`endif
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`endif
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wire MODER_Rd = MODER_Acc & ~RW;
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wire MODER_Rd = MODER_Acc & ~rw;
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wire RISCOP_Rd = RISCOP_Acc & ~RW;
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wire RISCOP_Rd = RISCOP_Acc & ~rw;
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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wire TSEL_Rd = TSEL_Acc & ~RW;
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wire TSEL_Rd = TSEL_Acc & ~rw;
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wire QSEL_Rd = QSEL_Acc & ~RW;
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wire QSEL_Rd = QSEL_Acc & ~rw;
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wire SSEL_Rd = SSEL_Acc & ~RW;
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wire SSEL_Rd = SSEL_Acc & ~rw;
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wire RECSEL_Rd = RECSEL_Acc & ~RW;
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wire RECSEL_Rd = RECSEL_Acc & ~rw;
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`endif
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`endif
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [1:1] RISCOPOut;
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wire [1:1] RISCOPOut;
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assign MODEROut[31:0] = 32'h0000;
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assign MODEROut[31:0] = 32'h0000;
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`endif
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`endif
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reg RiscStallBp;
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reg RiscStallBp;
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always @(posedge Clk or posedge Reset)
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always @(posedge clk or posedge reset)
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begin
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begin
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if(Reset)
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if(reset)
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RiscStallBp <= 1'b0;
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RiscStallBp <= 1'b0;
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else
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else
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if(Bp) // Breakpoint sets bit
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if(bp) // Breakpoint sets bit
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RiscStallBp <= 1'b1;
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RiscStallBp <= 1'b1;
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else
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else
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if(RISCOP_Wr) // Register access can set or clear bit
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if(RISCOP_Wr) // Register access can set or clear bit
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RiscStallBp <= DataIn[0];
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RiscStallBp <= data_in[0];
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end
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end
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dbg_register #(1) RISCOP (.DataIn(DataIn[1]), .DataOut(RISCOPOut[1]), .Write(RISCOP_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
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dbg_register #(1) RISCOP (.data_in(data_in[1]), .data_out(RISCOPOut[1]), .write(RISCOP_Wr), .clk(clk), .reset(reset), .defaulty(1'b0));
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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dbg_register #(2) MODER (.DataIn(DataIn[17:16]), .DataOut(MODEROut[17:16]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
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dbg_register #(2) MODER (.data_in(data_in[17:16]), .data_out(MODEROut[17:16]), .write(MODER_Wr), .clk(clk), .reset(reset), .defaulty(`MODER_DEF));
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dbg_register #(32) TSEL (.DataIn(DataIn), .DataOut(TSELOut), .Write(TSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`TSEL_DEF));
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dbg_register #(32) TSEL (.data_in(data_in), .data_out(TSELOut), .write(TSEL_Wr), .clk(clk), .reset(reset), .defaulty(`TSEL_DEF));
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dbg_register #(32) QSEL (.DataIn(DataIn), .DataOut(QSELOut), .Write(QSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`QSEL_DEF));
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dbg_register #(32) QSEL (.data_in(data_in), .data_out(QSELOut), .write(QSEL_Wr), .clk(clk), .reset(reset), .defaulty(`QSEL_DEF));
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dbg_register #(32) SSEL (.DataIn(DataIn), .DataOut(SSELOut), .Write(SSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`SSEL_DEF));
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dbg_register #(32) SSEL (.data_in(data_in), .data_out(SSELOut), .write(SSEL_Wr), .clk(clk), .reset(reset), .defaulty(`SSEL_DEF));
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dbg_register #(7) RECSEL (.DataIn(DataIn[6:0]), .DataOut(RECSELOut), .Write(RECSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECSEL_DEF));
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dbg_register #(7) RECSEL (.data_in(data_in[6:0]), .data_out(RECSELOut), .write(RECSEL_Wr), .clk(clk), .reset(reset), .defaulty(`RECSEL_DEF));
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`endif
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`endif
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always @ (posedge Clk)
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always @ (posedge clk)
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begin
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begin
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if(MODER_Rd) DataOut<= #Tp MODEROut;
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if(MODER_Rd) data_out<= #Tp MODEROut;
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else
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else
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if(RISCOP_Rd) DataOut<= #Tp {30'h0, RISCOPOut[1], RiscStall};
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if(RISCOP_Rd) data_out<= #Tp {30'h0, RISCOPOut[1], risc_stall};
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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else
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else
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if(TSEL_Rd) DataOut<= #Tp TSELOut;
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if(TSEL_Rd) data_out<= #Tp TSELOut;
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else
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else
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if(QSEL_Rd) DataOut<= #Tp QSELOut;
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if(QSEL_Rd) data_out<= #Tp QSELOut;
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else
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else
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if(SSEL_Rd) DataOut<= #Tp SSELOut;
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if(SSEL_Rd) data_out<= #Tp SSELOut;
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else
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else
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if(RECSEL_Rd) DataOut<= #Tp {25'h0, RECSELOut};
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if(RECSEL_Rd) data_out<= #Tp {25'h0, RECSELOut};
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`endif
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`endif
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else DataOut<= #Tp 'h0;
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else data_out<= #Tp 'h0;
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end
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end
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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assign TraceEnable = MODEROut[16];
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assign TraceEnable = MODEROut[16];
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assign ContinMode = MODEROut[17];
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assign ContinMode = MODEROut[17];
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assign RecordReadSPR = RECSELOut[4];
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assign RecordReadSPR = RECSELOut[4];
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assign RecordWriteSPR = RECSELOut[5];
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assign RecordWriteSPR = RECSELOut[5];
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assign RecordINSTR = RECSELOut[6];
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assign RecordINSTR = RECSELOut[6];
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`endif
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`endif
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assign RiscStall = Bp | RiscStallBp; // Bp asynchronously sets the RiscStall, then RiscStallBp (from register) holds it active
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assign risc_stall = bp | RiscStallBp; // bp asynchronously sets the risc_stall, then RiscStallBp (from register) holds it active
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assign RiscReset = RISCOPOut[1];
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assign risc_reset = RISCOPOut[1];
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endmodule
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endmodule
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