URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_sync_clk1_clk2.v] - Diff between revs 17 and 20

Rev 17	Rev 20
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2001/10/19 11:40:01 mohor`
	`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
	`// few different cores in a single project.`
	`//`
`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
`// Initial official release.`	`// Initial official release.`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
	`// synopsys translate_on`

`// FF in clock domain 1 is being set by a signal from the clock domain 2`	`// FF in clock domain 1 is being set by a signal from the clock domain 2`
`module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);`	`module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);`

`parameter Tp = 1;`	`parameter Tp = 1;`