| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9 2001/10/19 11:40:01 mohor
|
|
// dbg_timescale.v changed to timescale.v This is done for the simulation of
|
|
// few different cores in a single project.
|
|
//
|
// Revision 1.8 2001/10/17 10:39:03 mohor
|
// Revision 1.8 2001/10/17 10:39:03 mohor
|
// bs_chain_o added.
|
// bs_chain_o added.
|
//
|
//
|
// Revision 1.7 2001/10/16 10:09:56 mohor
|
// Revision 1.7 2001/10/16 10:09:56 mohor
|
// Signal names changed to lowercase.
|
// Signal names changed to lowercase.
|
| Line 217... |
Line 221... |
reg WBErrorLatch; // Error latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
|
|
wire TCK = tck_pad_i;
|
wire TCK = tck_pad_i;
|
wire TMS = tms_pad_i;
|
wire TMS = tms_pad_i;
|
wire TDI = tdi_pad_i;
|
wire TDI = tdi_pad_i;
|
wire RESET = ~trst_pad_i | wb_rst_i; // trst_pad_i is active low
|
wire trst = ~trst_pad_i; // trst_pad_i is active low
|
|
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
|
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
| Line 315... |
Line 319... |
* TAP State Machine: Fully JTAG compliant *
|
* TAP State Machine: Fully JTAG compliant *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
// TestLogicReset state
|
// TestLogicReset state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
TestLogicReset<=#Tp 1;
|
TestLogicReset<=#Tp 1;
|
else
|
else
|
begin
|
begin
|
if(TMS & (TestLogicReset | SelectIRScan))
|
if(TMS & (TestLogicReset | SelectIRScan))
|
TestLogicReset<=#Tp 1;
|
TestLogicReset<=#Tp 1;
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| Line 329... |
Line 333... |
TestLogicReset<=#Tp 0;
|
TestLogicReset<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// RunTestIdle state
|
// RunTestIdle state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
RunTestIdle<=#Tp 0;
|
RunTestIdle<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
|
if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
|
RunTestIdle<=#Tp 1;
|
RunTestIdle<=#Tp 1;
|
| Line 343... |
Line 347... |
RunTestIdle<=#Tp 0;
|
RunTestIdle<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// SelectDRScan state
|
// SelectDRScan state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
SelectDRScan<=#Tp 0;
|
SelectDRScan<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
|
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
|
SelectDRScan<=#Tp 1;
|
SelectDRScan<=#Tp 1;
|
| Line 357... |
Line 361... |
SelectDRScan<=#Tp 0;
|
SelectDRScan<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// CaptureDR state
|
// CaptureDR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
CaptureDR<=#Tp 0;
|
CaptureDR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & SelectDRScan)
|
if(~TMS & SelectDRScan)
|
CaptureDR<=#Tp 1;
|
CaptureDR<=#Tp 1;
|
| Line 371... |
Line 375... |
CaptureDR<=#Tp 0;
|
CaptureDR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// ShiftDR state
|
// ShiftDR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
ShiftDR<=#Tp 0;
|
ShiftDR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
|
if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
|
ShiftDR<=#Tp 1;
|
ShiftDR<=#Tp 1;
|
| Line 385... |
Line 389... |
ShiftDR<=#Tp 0;
|
ShiftDR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// Exit1DR state
|
// Exit1DR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
Exit1DR<=#Tp 0;
|
Exit1DR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & (CaptureDR | ShiftDR))
|
if(TMS & (CaptureDR | ShiftDR))
|
Exit1DR<=#Tp 1;
|
Exit1DR<=#Tp 1;
|
| Line 399... |
Line 403... |
Exit1DR<=#Tp 0;
|
Exit1DR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// PauseDR state
|
// PauseDR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
PauseDR<=#Tp 0;
|
PauseDR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & (Exit1DR | PauseDR))
|
if(~TMS & (Exit1DR | PauseDR))
|
PauseDR<=#Tp 1;
|
PauseDR<=#Tp 1;
|
| Line 413... |
Line 417... |
PauseDR<=#Tp 0;
|
PauseDR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// Exit2DR state
|
// Exit2DR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
Exit2DR<=#Tp 0;
|
Exit2DR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & PauseDR)
|
if(TMS & PauseDR)
|
Exit2DR<=#Tp 1;
|
Exit2DR<=#Tp 1;
|
| Line 427... |
Line 431... |
Exit2DR<=#Tp 0;
|
Exit2DR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// UpdateDR state
|
// UpdateDR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
UpdateDR<=#Tp 0;
|
UpdateDR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & (Exit1DR | Exit2DR))
|
if(TMS & (Exit1DR | Exit2DR))
|
UpdateDR<=#Tp 1;
|
UpdateDR<=#Tp 1;
|
| Line 449... |
Line 453... |
UpdateDR_q<=#Tp UpdateDR;
|
UpdateDR_q<=#Tp UpdateDR;
|
end
|
end
|
|
|
|
|
// SelectIRScan state
|
// SelectIRScan state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
SelectIRScan<=#Tp 0;
|
SelectIRScan<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & SelectDRScan)
|
if(TMS & SelectDRScan)
|
SelectIRScan<=#Tp 1;
|
SelectIRScan<=#Tp 1;
|
| Line 463... |
Line 467... |
SelectIRScan<=#Tp 0;
|
SelectIRScan<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// CaptureIR state
|
// CaptureIR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
CaptureIR<=#Tp 0;
|
CaptureIR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & SelectIRScan)
|
if(~TMS & SelectIRScan)
|
CaptureIR<=#Tp 1;
|
CaptureIR<=#Tp 1;
|
| Line 477... |
Line 481... |
CaptureIR<=#Tp 0;
|
CaptureIR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// ShiftIR state
|
// ShiftIR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
ShiftIR<=#Tp 0;
|
ShiftIR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
|
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
|
ShiftIR<=#Tp 1;
|
ShiftIR<=#Tp 1;
|
| Line 491... |
Line 495... |
ShiftIR<=#Tp 0;
|
ShiftIR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// Exit1IR state
|
// Exit1IR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
Exit1IR<=#Tp 0;
|
Exit1IR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & (CaptureIR | ShiftIR))
|
if(TMS & (CaptureIR | ShiftIR))
|
Exit1IR<=#Tp 1;
|
Exit1IR<=#Tp 1;
|
| Line 505... |
Line 509... |
Exit1IR<=#Tp 0;
|
Exit1IR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// PauseIR state
|
// PauseIR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
PauseIR<=#Tp 0;
|
PauseIR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(~TMS & (Exit1IR | PauseIR))
|
if(~TMS & (Exit1IR | PauseIR))
|
PauseIR<=#Tp 1;
|
PauseIR<=#Tp 1;
|
| Line 519... |
Line 523... |
PauseIR<=#Tp 0;
|
PauseIR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// Exit2IR state
|
// Exit2IR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
Exit2IR<=#Tp 0;
|
Exit2IR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & PauseIR)
|
if(TMS & PauseIR)
|
Exit2IR<=#Tp 1;
|
Exit2IR<=#Tp 1;
|
| Line 533... |
Line 537... |
Exit2IR<=#Tp 0;
|
Exit2IR<=#Tp 0;
|
end
|
end
|
end
|
end
|
|
|
// UpdateIR state
|
// UpdateIR state
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
UpdateIR<=#Tp 0;
|
UpdateIR<=#Tp 0;
|
else
|
else
|
begin
|
begin
|
if(TMS & (Exit1IR | Exit2IR))
|
if(TMS & (Exit1IR | Exit2IR))
|
UpdateIR<=#Tp 1;
|
UpdateIR<=#Tp 1;
|
| Line 566... |
Line 570... |
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
|
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
|
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
|
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
|
|
|
reg TDOInstruction;
|
reg TDOInstruction;
|
|
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
|
else
|
else
|
begin
|
begin
|
if(CaptureIR)
|
if(CaptureIR)
|
begin
|
begin
|
| Line 613... |
Line 617... |
|
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg TDOData;
|
reg TDOData;
|
|
|
|
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
else
|
else
|
if(ShiftDR)
|
if(ShiftDR)
|
JTAG_DR_IN[BitCounter]<=#Tp TDI;
|
JTAG_DR_IN[BitCounter]<=#Tp TDI;
|
end
|
end
|
| Line 637... |
Line 641... |
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
`endif
|
`endif
|
|
|
//TDO is changing on the falling edge of TCK
|
//TDO is changing on the falling edge of TCK
|
always @ (negedge TCK or posedge RESET)
|
always @ (negedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
begin
|
begin
|
TDOData <= #Tp 0;
|
TDOData <= #Tp 0;
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
ReadBuffer_Tck<=#Tp 0;
|
ReadBuffer_Tck<=#Tp 0;
|
`endif
|
`endif
|
| Line 705... |
Line 709... |
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* CHAIN_SELECT logic *
|
* CHAIN_SELECT logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
else
|
else
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
|
end
|
end
|
| Line 722... |
Line 726... |
* *
|
* *
|
* Register read/write logic *
|
* Register read/write logic *
|
* RISC registers read/write logic *
|
* RISC registers read/write logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
begin
|
begin
|
ADDR[31:0] <=#Tp 32'h0;
|
ADDR[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
RW <=#Tp 1'b0;
|
RW <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
RegAccessTck <=#Tp 1'b0;
|
| Line 776... |
Line 780... |
assign wb_sel_o[3:0] = 4'hf;
|
assign wb_sel_o[3:0] = 4'hf;
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
|
|
|
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
);
|
);
|
|
|
|
|
// Synchronizing the wb_Access signal to wishbone clock
|
// Synchronizing the wb_Access signal to wishbone clock
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
// Delayed signals used for accessing registers and RISC
|
// Delayed signals used for accessing registers and RISC
|
always @ (posedge risc_clk_i or posedge RESET)
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(RESET)
|
if(wb_rst_i)
|
begin
|
begin
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RegAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
RISCAccess_q <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
RISCAccess_q2 <=#Tp 1'b0;
|
| Line 816... |
Line 820... |
end
|
end
|
end
|
end
|
|
|
|
|
// Latching data read from registers
|
// Latching data read from registers
|
always @ (posedge risc_clk_i or posedge RESET)
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(RESET)
|
if(wb_rst_i)
|
RegisterReadLatch[31:0]<=#Tp 0;
|
RegisterReadLatch[31:0]<=#Tp 0;
|
else
|
else
|
if(RegAccess_q & ~RegAccess_q2)
|
if(RegAccess_q & ~RegAccess_q2)
|
RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
|
end
|
end
|
| Line 834... |
Line 838... |
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
|
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
|
|
|
|
|
reg wb_Access_wbClk_q;
|
reg wb_Access_wbClk_q;
|
// Delayed signals used for accessing WISHBONE
|
// Delayed signals used for accessing WISHBONE
|
always @ (posedge wb_clk_i or posedge RESET)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
|
begin
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if(RESET)
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if(wb_rst_i)
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wb_Access_wbClk_q <=#Tp 1'b0;
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wb_Access_wbClk_q <=#Tp 1'b0;
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else
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else
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wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
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wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
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end
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end
|
|
|
always @ (posedge wb_clk_i or posedge RESET)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(RESET)
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if(wb_rst_i)
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wb_cyc_o <=#Tp 1'b0;
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wb_cyc_o <=#Tp 1'b0;
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else
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else
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if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
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if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
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wb_cyc_o <=#Tp 1'b1;
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wb_cyc_o <=#Tp 1'b1;
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else
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else
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| Line 858... |
Line 862... |
|
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assign wb_stb_o = wb_cyc_o;
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assign wb_stb_o = wb_cyc_o;
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|
|
|
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// Latching data read from registers
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// Latching data read from registers
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always @ (posedge risc_clk_i or posedge RESET)
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always @ (posedge risc_clk_i or posedge wb_rst_i)
|
begin
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begin
|
if(RESET)
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if(wb_rst_i)
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WBReadLatch[31:0]<=#Tp 32'h0;
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WBReadLatch[31:0]<=#Tp 32'h0;
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else
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else
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if(wb_ack_i)
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if(wb_ack_i)
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WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
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WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
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end
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end
|
|
|
// Latching WISHBONE error cycle
|
// Latching WISHBONE error cycle
|
always @ (posedge wb_clk_i or posedge RESET)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(RESET)
|
if(wb_rst_i)
|
WBErrorLatch<=#Tp 1'b0;
|
WBErrorLatch<=#Tp 1'b0;
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else
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else
|
if(wb_err_i)
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if(wb_err_i)
|
WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
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WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
|
if(wb_ack_i)
|
if(wb_ack_i)
|
| Line 912... |
Line 916... |
end
|
end
|
|
|
|
|
|
|
// Latching data read from RISC
|
// Latching data read from RISC
|
always @ (posedge risc_clk_i or posedge RESET)
|
always @ (posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(RESET)
|
if(wb_rst_i)
|
RISC_DATAINLatch[31:0]<=#Tp 0;
|
RISC_DATAINLatch[31:0]<=#Tp 0;
|
else
|
else
|
if(RISCAccess_q & ~RISCAccess_q2)
|
if(RISCAccess_q & ~RISCAccess_q2)
|
RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
|
RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
|
end
|
end
|
| Line 935... |
Line 939... |
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
);
|
);
|
|
|
|
|
|
|
always @(posedge risc_clk_i or posedge RESET)
|
always @(posedge risc_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(RESET)
|
if(wb_rst_i)
|
ReadTraceBuffer_q <=#Tp 0;
|
ReadTraceBuffer_q <=#Tp 0;
|
else
|
else
|
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
|
end
|
end
|
|
|
| Line 995... |
Line 999... |
* Activating Instructions *
|
* Activating Instructions *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
// Updating JTAG_IR (Instruction Register)
|
// Updating JTAG_IR (Instruction Register)
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
|
LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
|
else
|
else
|
if(UpdateIR)
|
if(UpdateIR)
|
LatchedJTAG_IR <=#Tp JTAG_IR;
|
LatchedJTAG_IR <=#Tp JTAG_IR;
|
end
|
end
|
| Line 1099... |
Line 1103... |
* Bit counter *
|
* Bit counter *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
BitCounter[7:0]<=#Tp 0;
|
BitCounter[7:0]<=#Tp 0;
|
else
|
else
|
if(ShiftDR)
|
if(ShiftDR)
|
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
|
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
|
else
|
else
|
| Line 1163... |
Line 1167... |
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Connecting CRC module *
|
* Connecting CRC module *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
wire AsyncResetCrc = RESET;
|
wire AsyncResetCrc = trst;
|
wire SyncResetCrc = UpdateDR_q;
|
wire SyncResetCrc = UpdateDR_q;
|
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
|
|
|
wire EnableCrcIn = ShiftDR &
|
wire EnableCrcIn = ShiftDR &
|
( (CHAIN_SELECTSelected & (BitCounter<4)) |
|
( (CHAIN_SELECTSelected & (BitCounter<4)) |
|
| Line 1195... |
Line 1199... |
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
.CrcOut(CalculatedCrcOut), .Clk(TCK));
|
.CrcOut(CalculatedCrcOut), .Clk(TCK));
|
|
|
|
|
// Generating CrcMatch signal
|
// Generating CrcMatch signal
|
always @ (posedge TCK or posedge RESET)
|
always @ (posedge TCK or posedge trst)
|
begin
|
begin
|
if(RESET)
|
if(trst)
|
CrcMatch <=#Tp 1'b0;
|
CrcMatch <=#Tp 1'b0;
|
else
|
else
|
if(Exit1DR)
|
if(Exit1DR)
|
begin
|
begin
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
| Line 1240... |
Line 1244... |
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
|
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
|
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
|
.Mclk(risc_clk_i), .Reset(RESET), .TraceChain(TraceChain),
|
.Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
|
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
|
.WpTrigger(WpTrigger),
|
.WpTrigger(WpTrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
|
