URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Diff between revs 18 and 19

Rev 18	Rev 19
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.10 2001/11/12 01:11:27 mohor`
	`// Reset signals are not combined any more.`
	`//`
`// Revision 1.9 2001/10/19 11:40:01 mohor`	`// Revision 1.9 2001/10/19 11:40:01 mohor`
`// dbg_timescale.v changed to timescale.v This is done for the simulation of`	`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
`// few different cores in a single project.`	`// few different cores in a single project.`
`//`	`//`
`// Revision 1.8 2001/10/17 10:39:03 mohor`	`// Revision 1.8 2001/10/17 10:39:03 mohor`
Line 862...	Line 865...

`assign wb_stb_o = wb_cyc_o;`	`assign wb_stb_o = wb_cyc_o;`


`// Latching data read from registers`	`// Latching data read from registers`
`always @ (posedge risc_clk_i or posedge wb_rst_i)`	`always @ (posedge wb_clk_i or posedge wb_rst_i)`
`begin`	`begin`
`if(wb_rst_i)`	`if(wb_rst_i)`
`WBReadLatch[31:0]<=#Tp 32'h0;`	`WBReadLatch[31:0]<=#Tp 32'h0;`
`else`	`else`
`if(wb_ack_i)`	`if(wb_ack_i)`