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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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//
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Reset signals are not combined any more.
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// Reset signals are not combined any more.
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//
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//
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// Revision 1.9 2001/10/19 11:40:01 mohor
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// Revision 1.9 2001/10/19 11:40:01 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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Line 90... |
// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
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// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
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// Initial release
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// Initial release
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "dbg_defines.v"
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`include "dbg_defines.v"
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// Top module
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// Top module
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module dbg_top(
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module dbg_top(
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// JTAG pins
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// JTAG pins
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Line 165... |
output wb_we_o;
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output wb_we_o;
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input wb_ack_i;
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input wb_ack_i;
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output wb_cab_o;
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output wb_cab_o;
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input wb_err_i;
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input wb_err_i;
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reg [31:0] wb_adr_o;
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reg [31:0] wb_dat_o;
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reg wb_we_o;
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reg wb_cyc_o;
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reg wb_cyc_o;
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// TAP states
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// TAP states
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reg TestLogicReset;
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reg TestLogicReset;
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reg RunTestIdle;
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reg RunTestIdle;
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Line 636... |
wire [72:0] RISC_Data;
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wire [72:0] RISC_Data;
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wire [45:0] Register_Data;
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wire [45:0] Register_Data;
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wire [72:0] WISHBONE_Data;
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wire [72:0] WISHBONE_Data;
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wire wb_Access_wbClk;
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wire wb_Access_wbClk;
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assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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assign WISHBONE_Data = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
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// assign WISHBONE_Data = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
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wire select_crc_out;
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assign select_crc_out = RegisterScanChain & JTAG_DR_IN[5] | // Calculated CRC is returned when read operation is
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RiscDebugScanChain & JTAG_DR_IN[32] | // performed, else received crc is returned (loopback).
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WishboneScanChain & JTAG_DR_IN[32] ;
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wire [8:0] send_crc;
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assign send_crc = select_crc_out? {9{JTAG_DR_IN[BitCounter-1]}} : // Calculated CRC is returned when read operation is
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{1'b0, CalculatedCrcOut} ; // performed, else received crc is returned (loopback).
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assign RISC_Data = {send_crc, RISC_DATAINLatch, 33'h0};
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assign Register_Data = {send_crc, RegisterReadLatch, 6'h0};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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assign Trace_Data = {CalculatedCrcOut, TraceChain};
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assign Trace_Data = {CalculatedCrcOut, TraceChain};
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`endif
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`endif
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| Line 738... |
Line 754... |
ADDR[31:0] <=#Tp 32'h0;
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ADDR[31:0] <=#Tp 32'h0;
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DataOut[31:0] <=#Tp 32'h0;
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DataOut[31:0] <=#Tp 32'h0;
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RW <=#Tp 1'b0;
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RW <=#Tp 1'b0;
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RegAccessTck <=#Tp 1'b0;
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RegAccessTck <=#Tp 1'b0;
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RISCAccessTck <=#Tp 1'b0;
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RISCAccessTck <=#Tp 1'b0;
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wb_adr_o <=#Tp 32'h0;
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wb_we_o <=#Tp 1'h0;
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wb_dat_o <=#Tp 32'h0;
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wb_AccessTck <=#Tp 1'h0;
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wb_AccessTck <=#Tp 1'h0;
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end
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end
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else
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else
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if(UpdateDR & DEBUGSelected & CrcMatch)
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if(UpdateDR & DEBUGSelected & CrcMatch)
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begin
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begin
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Line 777... |
RISCAccessTck <=#Tp 1'b1;
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RISCAccessTck <=#Tp 1'b1;
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end
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end
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else
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else
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if(WishboneScanChain)
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if(WishboneScanChain)
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begin
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begin
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wb_adr_o <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
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ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
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wb_we_o <=#Tp JTAG_DR_IN[32]; // latch R/W bit
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RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
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wb_dat_o <=#Tp JTAG_DR_IN[64:33]; // latch data for write
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DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
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wb_AccessTck <=#Tp 1'b1; //
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wb_AccessTck <=#Tp 1'b1; //
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end
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end
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end
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end
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else
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else
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begin
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begin
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| Line 778... |
Line 791... |
RISCAccessTck <=#Tp 1'b0;
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RISCAccessTck <=#Tp 1'b0;
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wb_AccessTck <=#Tp 1'b0;
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wb_AccessTck <=#Tp 1'b0;
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end
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end
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end
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end
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assign wb_adr_o = ADDR;
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assign wb_we_o = RW;
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assign wb_dat_o = DataOut;
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assign wb_sel_o[3:0] = 4'hf;
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assign wb_sel_o[3:0] = 4'hf;
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assign wb_cab_o = 1'b0;
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assign wb_cab_o = 1'b0;
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// Synchronizing the RegAccess signal to risc_clk_i clock
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// Synchronizing the RegAccess signal to risc_clk_i clock
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Line 899... |
if(wb_rst_i)
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if(wb_rst_i)
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WBErrorLatch<=#Tp 1'b0;
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WBErrorLatch<=#Tp 1'b0;
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else
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else
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if(wb_err_i)
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if(wb_err_i)
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WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
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WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
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else
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if(wb_ack_i)
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if(wb_ack_i)
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WBErrorLatch<=#Tp 1'b0; // Clearing status
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WBErrorLatch<=#Tp 1'b0; // Clearing status
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end
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end
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