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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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//
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Revision 1.11 2001/11/14 10:10:41 mohor
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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// Wishbone data latched on wb_clk_i instead of risc_clk.
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//
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//
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Revision 1.10 2001/11/12 01:11:27 mohor
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// Reset signals are not combined any more.
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// Reset signals are not combined any more.
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| Line 634... |
Line 637... |
end
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end
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wire [72:0] RISC_Data;
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wire [72:0] RISC_Data;
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wire [45:0] Register_Data;
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wire [45:0] Register_Data;
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wire [72:0] WISHBONE_Data;
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wire [72:0] WISHBONE_Data;
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wire [12:0] chain_sel_data;
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wire wb_Access_wbClk;
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wire wb_Access_wbClk;
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// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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// assign WISHBONE_Data = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
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// assign WISHBONE_Data = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
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wire select_crc_out;
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wire select_crc_out;
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assign select_crc_out = RegisterScanChain & JTAG_DR_IN[5] | // Calculated CRC is returned when read operation is
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assign select_crc_out = RegisterScanChain & JTAG_DR_IN[5] | // Calculated CRC is returned when read operation is
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RiscDebugScanChain & JTAG_DR_IN[32] | // performed, else received crc is returned (loopback).
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RiscDebugScanChain & JTAG_DR_IN[32] | // performed, else received crc is returned (loopback).
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WishboneScanChain & JTAG_DR_IN[32] ;
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WishboneScanChain & JTAG_DR_IN[32] |
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CHAIN_SELECTSelected; // When chain is selected, received crc is returned
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wire [8:0] send_crc;
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wire [8:0] send_crc;
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assign send_crc = select_crc_out? {9{JTAG_DR_IN[BitCounter-1]}} : // Calculated CRC is returned when read operation is
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assign send_crc = select_crc_out? {9{JTAG_DR_IN[BitCounter-1]}} : // Calculated CRC is returned when read operation is
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{1'b0, CalculatedCrcOut} ; // performed, else received crc is returned (loopback).
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{1'b0, CalculatedCrcOut} ; // performed, else received crc is returned (loopback).
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assign RISC_Data = {send_crc, RISC_DATAINLatch, 33'h0};
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assign RISC_Data = {send_crc, RISC_DATAINLatch, 33'h0};
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assign Register_Data = {send_crc, RegisterReadLatch, 6'h0};
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assign Register_Data = {send_crc, RegisterReadLatch, 6'h0};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
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assign chain_sel_data = {send_crc, 4'h0};
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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assign Trace_Data = {CalculatedCrcOut, TraceChain};
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assign Trace_Data = {CalculatedCrcOut, TraceChain};
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`endif
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`endif
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Line 692... |
begin
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begin
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if(IDCODESelected)
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if(IDCODESelected)
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TDOData <= #Tp IDCodeValue[BitCounter]; // IDCODE is shifted out
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TDOData <= #Tp IDCodeValue[BitCounter]; // IDCODE is shifted out
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else
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else
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if(CHAIN_SELECTSelected)
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if(CHAIN_SELECTSelected)
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TDOData <= #Tp 0;
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TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
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else
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else
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if(DEBUGSelected)
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if(DEBUGSelected)
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begin
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begin
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if(RiscDebugScanChain)
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if(RiscDebugScanChain)
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TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
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TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
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