| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Register length fixed.
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//
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// Revision 1.13 2001/11/27 13:37:43 mohor
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// CRC is returned when chain selection data is transmitted.
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// CRC is returned when chain selection data is transmitted.
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//
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//
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Revision 1.12 2001/11/26 10:47:09 mohor
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// Crc generation is different for read or write commands. Small synthesys fixes.
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// Crc generation is different for read or write commands. Small synthesys fixes.
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Line 231... |
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
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reg RISCAccess_q2; // Delayed signals used for accessing the RISC
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg trst; // trst is active high while trst_pad_i is active low
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wire TCK = tck_pad_i;
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wire TCK = tck_pad_i;
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wire TMS = tms_pad_i;
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wire TMS = tms_pad_i;
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wire TDI = tdi_pad_i;
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wire TDI = tdi_pad_i;
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wire trst = ~trst_pad_i; // trst_pad_i is active low
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wire [31:0] RegDataIn; // Data from registers (read data)
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wire [31:0] RegDataIn; // Data from registers (read data)
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wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
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wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
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wire RiscStall_reg; // RISC is stalled by setting the register bit
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wire RiscStall_reg; // RISC is stalled by setting the register bit
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| Line 325... |
Line 328... |
`endif
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`endif
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/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* Synchronizing TRST to clock signal *
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* *
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**********************************************************************************/
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always @ (posedge wb_clk_i)
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begin
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trst <=#Tp ~trst_pad_i; // trst_pad_i is active low
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end
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/**********************************************************************************
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* *
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* TAP State Machine: Fully JTAG compliant *
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* TAP State Machine: Fully JTAG compliant *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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// TestLogicReset state
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// TestLogicReset state
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