| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2001/12/20 11:17:26 mohor
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// TDO and TDO Enable signal are separated into two signals.
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//
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// Revision 1.15 2001/12/05 13:28:21 mohor
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// Revision 1.15 2001/12/05 13:28:21 mohor
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// trst signal is synchronized to wb_clk_i.
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// trst signal is synchronized to wb_clk_i.
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//
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//
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Revision 1.14 2001/11/28 09:36:15 mohor
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// Register length fixed.
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// Register length fixed.
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| Line 218... |
Line 221... |
reg [31:0] DataOut;
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reg [31:0] DataOut;
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reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
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reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
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reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
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reg [31:0] RISC_DATAINLatch; // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is
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reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
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// accessed for reading
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reg [31:0] RegisterReadLatch; // Data when reading register is latched one TCK clock after the register is read.
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reg RegAccessTck; // Indicates access to the registers (read or write)
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reg RegAccessTck; // Indicates access to the registers (read or write)
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reg RISCAccessTck; // Indicates access to the RISC (read or write)
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reg RISCAccessTck; // Indicates access to the RISC (read or write)
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reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
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reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
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reg RW; // Read/Write bit
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reg RW; // Read/Write bit
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reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
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reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
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| Line 237... |
Line 238... |
reg wb_AccessTck; // Indicates access to the WISHBONE
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reg wb_AccessTck; // Indicates access to the WISHBONE
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg [31:0] WBReadLatch; // Data latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg WBErrorLatch; // Error latched during WISHBONE read
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reg trst; // trst is active high while trst_pad_i is active low
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reg trst; // trst is active high while trst_pad_i is active low
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reg BypassRegister; // Bypass register
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wire TCK = tck_pad_i;
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wire TCK = tck_pad_i;
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wire TMS = tms_pad_i;
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wire TMS = tms_pad_i;
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wire TDI = tdi_pad_i;
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wire TDI = tdi_pad_i;
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wire [31:0] RegDataIn; // Data from registers (read data)
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wire [31:0] RegDataIn; // Data from registers (read data)
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| Line 257... |
Line 261... |
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wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
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wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
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wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
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wire RiscStall_access; // Stalling RISC because of the read or write access
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wire RiscStall_access; // Stalling RISC because of the read or write access
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wire BitCounter_Lt4;
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wire BitCounter_Eq5;
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wire BitCounter_Eq32;
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wire BitCounter_Lt38;
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wire BitCounter_Lt65;
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assign capture_dr_o = CaptureDR;
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assign capture_dr_o = CaptureDR;
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assign shift_dr_o = ShiftDR;
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assign shift_dr_o = ShiftDR;
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assign update_dr_o = UpdateDR;
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assign update_dr_o = UpdateDR;
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assign extest_selected_o = EXTESTSelected;
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assign extest_selected_o = EXTESTSelected;
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| Line 326... |
Line 335... |
wire TraceTestScanChain; // Trace Test Scan chain selected
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wire TraceTestScanChain; // Trace Test Scan chain selected
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wire [47:0] Trace_Data; // Trace data
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wire [47:0] Trace_Data; // Trace data
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wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
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wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
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// data is set to the risc_data_i)
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// data is set to the risc_data_i)
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wire BitCounter_Lt40;
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`endif
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`endif
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/**********************************************************************************
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/**********************************************************************************
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| Line 640... |
Line 650... |
/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* JTAG_DR: JTAG Data Register *
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* JTAG_DR: JTAG Data Register *
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* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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wire [31:0] IDCodeValue = `IDCODE_VALUE; // IDCODE value is 32-bit long.
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reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
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reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
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reg TDOData;
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reg TDOData;
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always @ (posedge TCK or posedge trst)
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always @ (posedge TCK or posedge trst)
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begin
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begin
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if(trst)
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if(trst)
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JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
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JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
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else
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else
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if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
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begin
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if(ShiftDR)
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if(ShiftDR)
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JTAG_DR_IN[BitCounter]<=#Tp TDI;
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JTAG_DR_IN[31:0] <= #Tp {TDI, JTAG_DR_IN[31:1]};
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else
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JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
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end
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else
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if(CHAIN_SELECTSelected & ShiftDR)
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JTAG_DR_IN[12:0] <= #Tp {TDI, JTAG_DR_IN[12:1]};
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else
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if(DEBUGSelected & ShiftDR)
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begin
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if(RiscDebugScanChain | WishboneScanChain)
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JTAG_DR_IN[73:0] <= #Tp {TDI, JTAG_DR_IN[73:1]};
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else
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if(RegisterScanChain)
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JTAG_DR_IN[46:0] <= #Tp {TDI, JTAG_DR_IN[46:1]};
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end
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end
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end
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wire [73:0] RISC_Data;
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wire [73:0] RISC_Data;
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wire [46:0] Register_Data;
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wire [46:0] Register_Data;
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wire [73:0] WISHBONE_Data;
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wire [73:0] WISHBONE_Data;
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wire [12:0] chain_sel_data;
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wire [12:0] chain_sel_data;
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wire wb_Access_wbClk;
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wire wb_Access_wbClk;
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// assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
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// assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
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reg select_crc_out;
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// assign WISHBONE_Data = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
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always @ (posedge TCK or posedge trst)
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begin
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wire select_crc_out;
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if(trst)
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assign select_crc_out = RegisterScanChain & JTAG_DR_IN[5] | // Calculated CRC is returned when read operation is
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select_crc_out <= 0;
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RiscDebugScanChain & JTAG_DR_IN[32] | // performed, else received crc is returned (loopback).
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else
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WishboneScanChain & JTAG_DR_IN[32] |
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if( RegisterScanChain & BitCounter_Eq5 |
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CHAIN_SELECTSelected; // When chain is selected, received crc is returned
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RiscDebugScanChain & BitCounter_Eq32 |
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WishboneScanChain & BitCounter_Eq32 )
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select_crc_out <=#Tp TDI;
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else
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if(CHAIN_SELECTSelected)
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select_crc_out <=#Tp 1;
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else
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if(UpdateDR)
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select_crc_out <=#Tp 0;
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end
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wire [8:0] send_crc;
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wire [8:0] send_crc;
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assign send_crc = select_crc_out? {9{JTAG_DR_IN[BitCounter-1]}} : // Calculated CRC is returned when read operation is
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assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
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{1'b0, CalculatedCrcOut} ; // performed, else received crc is returned (loopback).
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{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
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assign RISC_Data = {send_crc, RISC_DATAINLatch, 33'h0};
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assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
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assign Register_Data = {send_crc, RegisterReadLatch, 6'h0};
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assign Register_Data = {send_crc, DataReadLatch, 6'h0};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
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assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
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assign chain_sel_data = {send_crc, 4'h0};
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assign chain_sel_data = {send_crc, 4'h0};
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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| Line 710... |
Line 744... |
else
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else
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begin
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begin
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if(ShiftDR)
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if(ShiftDR)
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begin
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begin
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if(IDCODESelected)
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if(IDCODESelected)
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TDOData <= #Tp IDCodeValue[BitCounter]; // IDCODE is shifted out
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TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then TDI is bypassed
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else
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else
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if(CHAIN_SELECTSelected)
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if(CHAIN_SELECTSelected)
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TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
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TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
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else
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else
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if(DEBUGSelected)
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if(DEBUGSelected)
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| Line 865... |
Line 899... |
RISCAccess_q <=#Tp RISCAccess;
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RISCAccess_q <=#Tp RISCAccess;
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RISCAccess_q2 <=#Tp RISCAccess_q;
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RISCAccess_q2 <=#Tp RISCAccess_q;
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end
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end
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end
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end
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// Latching data read from registers
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always @ (posedge risc_clk_i or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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RegisterReadLatch[31:0]<=#Tp 0;
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else
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if(RegAccess_q & ~RegAccess_q2)
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RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
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end
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// Chip select and read/write signals for accessing RISC
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// Chip select and read/write signals for accessing RISC
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assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
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assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
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assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
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assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
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assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
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assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
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| Line 962... |
Line 984... |
opselect_o = 3'h0;
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opselect_o = 3'h0;
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`endif
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`endif
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end
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end
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// Latching data read from RISC or registers
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// Latching data read from RISC
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always @ (posedge risc_clk_i or posedge wb_rst_i)
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always @ (posedge risc_clk_i or posedge wb_rst_i)
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begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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RISC_DATAINLatch[31:0]<=#Tp 0;
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DataReadLatch[31:0]<=#Tp 0;
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else
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else
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if(RISCAccess_q & ~RISCAccess_q2)
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if(RISCAccess_q & ~RISCAccess_q2)
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RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
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DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
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else
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if(RegAccess_q & ~RegAccess_q2)
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DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
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end
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end
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assign risc_addr_o = ADDR;
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assign risc_addr_o = ADDR;
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assign risc_data_o = DataOut;
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assign risc_data_o = DataOut;
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| Line 1017... |
Line 1041... |
/**********************************************************************************
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/**********************************************************************************
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* *
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* *
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* Bypass logic *
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* Bypass logic *
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* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
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reg BypassRegister;
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reg TDOBypassed;
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reg TDOBypassed;
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always @ (posedge TCK)
|
always @ (posedge TCK)
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begin
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begin
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if(ShiftDR)
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if(ShiftDR)
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| Line 1221... |
Line 1244... |
**********************************************************************************/
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**********************************************************************************/
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wire AsyncResetCrc = trst;
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wire AsyncResetCrc = trst;
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wire SyncResetCrc = UpdateDR_q;
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wire SyncResetCrc = UpdateDR_q;
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wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
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wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
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assign BitCounter_Lt4 = BitCounter<4;
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assign BitCounter_Eq5 = BitCounter==5;
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assign BitCounter_Eq32 = BitCounter==32;
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assign BitCounter_Lt38 = BitCounter<38;
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assign BitCounter_Lt65 = BitCounter<65;
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`ifdef TRACE_ENABLED
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assign BitCounter_Lt40 = BitCounter<40;
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`endif
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wire EnableCrcIn = ShiftDR &
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wire EnableCrcIn = ShiftDR &
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( (CHAIN_SELECTSelected & (BitCounter<4)) |
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( (CHAIN_SELECTSelected & BitCounter_Lt4) |
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((DEBUGSelected & RegisterScanChain) & (BitCounter<38)) |
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((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
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((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
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((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
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((DEBUGSelected & WishboneScanChain) & (BitCounter<65))
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((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
|
);
|
);
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|
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wire EnableCrcOut= ShiftDR &
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wire EnableCrcOut= ShiftDR &
|
(
|
(
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((DEBUGSelected & RegisterScanChain) & (BitCounter<38)) |
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((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
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((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
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((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
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((DEBUGSelected & WishboneScanChain) & (BitCounter<65))
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((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
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`ifdef TRACE_ENABLED
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`ifdef TRACE_ENABLED
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|
|
|
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((DEBUGSelected & TraceTestScanChain) & (BitCounter<40))
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((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
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`endif
|
`endif
|
);
|
);
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|
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// Calculating crc for input data
|
// Calculating crc for input data
|
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
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dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
| Line 1259... |
Line 1293... |
if(Exit1DR)
|
if(Exit1DR)
|
begin
|
begin
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
|
else
|
else
|
if(RegisterScanChain & ~CHAIN_SELECTSelected)
|
begin
|
|
if(RegisterScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
|
else
|
else
|
if(RiscDebugScanChain & ~CHAIN_SELECTSelected)
|
if(RiscDebugScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
else
|
else
|
if(WishboneScanChain & ~CHAIN_SELECTSelected)
|
if(WishboneScanChain)
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
|
end
|
end
|
end
|
end
|
|
end
|
|
|
|
|
// Active chain
|
// Active chain
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
|
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
|
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
|
