| Line 2... |
Line 2... |
//// ////
|
//// ////
|
//// dbg_top.v ////
|
//// dbg_top.v ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// This file is part of the SoC/OpenRISC Development Interface ////
|
//// http://www.opencores.org/cores/DebugInterface/ ////
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// Igor Mohor ////
|
//// Igor Mohor ////
|
//// igorm@opencores.org ////
|
//// igorm@opencores.org ////
|
| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.20 2002/02/06 12:23:09 mohor
|
|
// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
|
|
//
|
// Revision 1.19 2002/02/05 13:34:51 mohor
|
// Revision 1.19 2002/02/05 13:34:51 mohor
|
// Stupid bug that was entered by previous update fixed.
|
// Stupid bug that was entered by previous update fixed.
|
//
|
//
|
// Revision 1.18 2002/02/05 12:41:01 mohor
|
// Revision 1.18 2002/02/05 12:41:01 mohor
|
// trst synchronization is not needed and was removed.
|
// trst synchronization is not needed and was removed.
|
| Line 122... |
Line 125... |
// synopsys translate_on
|
// synopsys translate_on
|
`include "dbg_defines.v"
|
`include "dbg_defines.v"
|
|
|
// Top module
|
// Top module
|
module dbg_top(
|
module dbg_top(
|
// JTAG pins
|
|
tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
|
|
|
|
// Boundary Scan signals
|
|
capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i, bs_chain_o,
|
|
|
|
// RISC signals
|
// RISC signals
|
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
|
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
|
bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
|
bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
|
|
|
// WISHBONE common signals
|
// WISHBONE common signals
|
wb_rst_i, wb_clk_i,
|
wb_rst_i, wb_clk_i,
|
|
|
// WISHBONE master interface
|
// WISHBONE master interface
|
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
|
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
|
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
|
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
|
|
|
|
// TAP states
|
|
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
|
|
|
|
// Instructions
|
|
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
|
|
|
|
// TAP signals
|
|
trst, tck, tdi, TDOData,
|
|
|
|
BypassRegister
|
|
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
// JTAG pins
|
|
input tms_pad_i; // JTAG test mode select pad
|
|
input tck_pad_i; // JTAG test clock pad
|
|
input trst_pad_i; // JTAG test reset pad
|
|
input tdi_pad_i; // JTAG test data input pad
|
|
output tdo_pad_o; // JTAG test data output pad
|
|
output tdo_padoen_o; // Output enable for JTAG test data output pad
|
|
|
|
|
|
// Boundary Scan signals
|
|
output capture_dr_o;
|
|
output shift_dr_o;
|
|
output update_dr_o;
|
|
output extest_selected_o;
|
|
input bs_chain_i;
|
|
output bs_chain_o;
|
|
|
|
// RISC signals
|
// RISC signals
|
input risc_clk_i; // Master clock (RISC clock)
|
input risc_clk_i; // Master clock (RISC clock)
|
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
|
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
|
input [10:0] wp_i; // Watchpoint inputs
|
input [10:0] wp_i; // Watchpoint inputs
|
| Line 191... |
Line 183... |
output wb_we_o;
|
output wb_we_o;
|
input wb_ack_i;
|
input wb_ack_i;
|
output wb_cab_o;
|
output wb_cab_o;
|
input wb_err_i;
|
input wb_err_i;
|
|
|
reg wb_cyc_o;
|
|
|
|
// TAP states
|
// TAP states
|
reg TestLogicReset;
|
input ShiftDR;
|
reg RunTestIdle;
|
input Exit1DR;
|
reg SelectDRScan;
|
input UpdateDR;
|
reg CaptureDR;
|
input UpdateDR_q;
|
reg ShiftDR;
|
|
reg Exit1DR;
|
input trst;
|
reg PauseDR;
|
input tck;
|
reg Exit2DR;
|
input tdi;
|
reg UpdateDR;
|
|
|
input BypassRegister;
|
reg SelectIRScan;
|
|
reg CaptureIR;
|
output TDOData;
|
reg ShiftIR;
|
|
reg Exit1IR;
|
|
reg PauseIR;
|
|
reg Exit2IR;
|
|
reg UpdateIR;
|
|
|
|
|
|
// Defining which instruction is selected
|
// Defining which instruction is selected
|
reg EXTESTSelected;
|
input IDCODESelected;
|
reg SAMPLE_PRELOADSelected;
|
input CHAIN_SELECTSelected;
|
reg IDCODESelected;
|
input DEBUGSelected;
|
reg CHAIN_SELECTSelected;
|
|
reg INTESTSelected;
|
reg wb_cyc_o;
|
reg CLAMPSelected;
|
|
reg CLAMPZSelected;
|
|
reg HIGHZSelected;
|
|
reg DEBUGSelected;
|
|
reg BYPASSSelected;
|
|
|
|
reg [31:0] ADDR;
|
reg [31:0] ADDR;
|
reg [31:0] DataOut;
|
reg [31:0] DataOut;
|
|
|
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
|
| Line 246... |
Line 226... |
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
|
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
|
|
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg wb_AccessTck; // Indicates access to the WISHBONE
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
reg WBErrorLatch; // Error latched during WISHBONE read
|
wire trst; // trst is active high while trst_pad_i is active low
|
|
|
|
reg BypassRegister; // Bypass register
|
|
|
|
|
|
wire TCK = tck_pad_i;
|
|
wire TMS = tms_pad_i;
|
|
wire TDI = tdi_pad_i;
|
|
|
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [31:0] RegDataIn; // Data from registers (read data)
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
|
|
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
wire RiscStall_reg; // RISC is stalled by setting the register bit
|
| Line 277... |
Line 250... |
wire BitCounter_Eq5;
|
wire BitCounter_Eq5;
|
wire BitCounter_Eq32;
|
wire BitCounter_Eq32;
|
wire BitCounter_Lt38;
|
wire BitCounter_Lt38;
|
wire BitCounter_Lt65;
|
wire BitCounter_Lt65;
|
|
|
assign capture_dr_o = CaptureDR;
|
|
assign shift_dr_o = ShiftDR;
|
|
assign update_dr_o = UpdateDR;
|
|
assign extest_selected_o = EXTESTSelected;
|
|
wire BS_CHAIN_I = bs_chain_i;
|
|
assign bs_chain_o = tdi_pad_i;
|
|
|
|
|
|
// This signals are used only when TRACE is used in the design
|
// This signals are used only when TRACE is used in the design
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
wire [39:0] TraceChain; // Chain that comes from trace module
|
wire [39:0] TraceChain; // Chain that comes from trace module
|
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with TCK)
|
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with tck)
|
wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
|
wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
|
reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
|
reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
|
wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
|
wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
|
|
|
// Outputs from registers
|
// Outputs from registers
|
| Line 350... |
Line 317... |
wire BitCounter_Lt40;
|
wire BitCounter_Lt40;
|
|
|
`endif
|
`endif
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Synchronizing TRST to clock signal *
|
|
* *
|
|
**********************************************************************************/
|
|
assign trst = ~trst_pad_i; // trst_pad_i is active low
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* TAP State Machine: Fully JTAG compliant *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
// TestLogicReset state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
TestLogicReset<=#Tp 1;
|
|
else
|
|
begin
|
|
if(TMS & (TestLogicReset | SelectIRScan))
|
|
TestLogicReset<=#Tp 1;
|
|
else
|
|
TestLogicReset<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// RunTestIdle state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
RunTestIdle<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
|
|
RunTestIdle<=#Tp 1;
|
|
else
|
|
RunTestIdle<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// SelectDRScan state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
SelectDRScan<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
|
|
SelectDRScan<=#Tp 1;
|
|
else
|
|
SelectDRScan<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// CaptureDR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
CaptureDR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & SelectDRScan)
|
|
CaptureDR<=#Tp 1;
|
|
else
|
|
CaptureDR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// ShiftDR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
ShiftDR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
|
|
ShiftDR<=#Tp 1;
|
|
else
|
|
ShiftDR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// Exit1DR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
Exit1DR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & (CaptureDR | ShiftDR))
|
|
Exit1DR<=#Tp 1;
|
|
else
|
|
Exit1DR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// PauseDR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
PauseDR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & (Exit1DR | PauseDR))
|
|
PauseDR<=#Tp 1;
|
|
else
|
|
PauseDR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// Exit2DR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
Exit2DR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & PauseDR)
|
|
Exit2DR<=#Tp 1;
|
|
else
|
|
Exit2DR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// UpdateDR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
UpdateDR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & (Exit1DR | Exit2DR))
|
|
UpdateDR<=#Tp 1;
|
|
else
|
|
UpdateDR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// Delayed UpdateDR state
|
|
reg UpdateDR_q;
|
|
always @ (posedge TCK)
|
|
begin
|
|
UpdateDR_q<=#Tp UpdateDR;
|
|
end
|
|
|
|
|
|
// SelectIRScan state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
SelectIRScan<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & SelectDRScan)
|
|
SelectIRScan<=#Tp 1;
|
|
else
|
|
SelectIRScan<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// CaptureIR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
CaptureIR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & SelectIRScan)
|
|
CaptureIR<=#Tp 1;
|
|
else
|
|
CaptureIR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// ShiftIR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
ShiftIR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
|
|
ShiftIR<=#Tp 1;
|
|
else
|
|
ShiftIR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// Exit1IR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
Exit1IR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & (CaptureIR | ShiftIR))
|
|
Exit1IR<=#Tp 1;
|
|
else
|
|
Exit1IR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// PauseIR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
PauseIR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(~TMS & (Exit1IR | PauseIR))
|
|
PauseIR<=#Tp 1;
|
|
else
|
|
PauseIR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// Exit2IR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
Exit2IR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & PauseIR)
|
|
Exit2IR<=#Tp 1;
|
|
else
|
|
Exit2IR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
// UpdateIR state
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
UpdateIR<=#Tp 0;
|
|
else
|
|
begin
|
|
if(TMS & (Exit1IR | Exit2IR))
|
|
UpdateIR<=#Tp 1;
|
|
else
|
|
UpdateIR<=#Tp 0;
|
|
end
|
|
end
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* End: TAP State Machine *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* JTAG_IR: JTAG Instruction Register *
|
|
* *
|
|
**********************************************************************************/
|
|
wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
|
|
|
|
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
|
|
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
|
|
|
|
reg TDOInstruction;
|
|
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
|
|
else
|
|
begin
|
|
if(CaptureIR)
|
|
begin
|
|
JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection
|
|
JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
|
|
end
|
|
else
|
|
begin
|
|
if(ShiftIR)
|
|
begin
|
|
JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
//TDO is changing on the falling edge of TCK
|
|
always @ (negedge TCK)
|
|
begin
|
|
if(ShiftIR)
|
|
TDOInstruction <= #Tp JTAG_IR[0];
|
|
end
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* End: JTAG_IR *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* JTAG_DR: JTAG Data Register *
|
* JTAG_DR: JTAG Data Register *
|
| Line 661... |
Line 332... |
**********************************************************************************/
|
**********************************************************************************/
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
|
reg TDOData;
|
reg TDOData;
|
|
|
|
|
always @ (posedge TCK or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
|
else
|
else
|
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
|
begin
|
begin
|
if(ShiftDR)
|
if(ShiftDR)
|
JTAG_DR_IN[31:0] <= #Tp {TDI, JTAG_DR_IN[31:1]};
|
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
|
else
|
else
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
|
end
|
end
|
else
|
else
|
if(CHAIN_SELECTSelected & ShiftDR)
|
if(CHAIN_SELECTSelected & ShiftDR)
|
JTAG_DR_IN[12:0] <= #Tp {TDI, JTAG_DR_IN[12:1]};
|
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
|
else
|
else
|
if(DEBUGSelected & ShiftDR)
|
if(DEBUGSelected & ShiftDR)
|
begin
|
begin
|
if(RiscDebugScanChain | WishboneScanChain)
|
if(RiscDebugScanChain | WishboneScanChain)
|
JTAG_DR_IN[73:0] <= #Tp {TDI, JTAG_DR_IN[73:1]};
|
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
|
else
|
else
|
if(RegisterScanChain)
|
if(RegisterScanChain)
|
JTAG_DR_IN[46:0] <= #Tp {TDI, JTAG_DR_IN[46:1]};
|
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
|
end
|
end
|
end
|
end
|
|
|
wire [73:0] RISC_Data;
|
wire [73:0] RISC_Data;
|
wire [46:0] Register_Data;
|
wire [46:0] Register_Data;
|
| Line 695... |
Line 366... |
wire [12:0] chain_sel_data;
|
wire [12:0] chain_sel_data;
|
wire wb_Access_wbClk;
|
wire wb_Access_wbClk;
|
|
|
|
|
reg select_crc_out;
|
reg select_crc_out;
|
always @ (posedge TCK or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
select_crc_out <= 0;
|
select_crc_out <= 0;
|
else
|
else
|
if( RegisterScanChain & BitCounter_Eq5 |
|
if( RegisterScanChain & BitCounter_Eq5 |
|
RiscDebugScanChain & BitCounter_Eq32 |
|
RiscDebugScanChain & BitCounter_Eq32 |
|
WishboneScanChain & BitCounter_Eq32 )
|
WishboneScanChain & BitCounter_Eq32 )
|
select_crc_out <=#Tp TDI;
|
select_crc_out <=#Tp tdi;
|
else
|
else
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
select_crc_out <=#Tp 1;
|
select_crc_out <=#Tp 1;
|
else
|
else
|
if(UpdateDR)
|
if(UpdateDR)
|
| Line 727... |
Line 398... |
|
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
assign Trace_Data = {CalculatedCrcOut, TraceChain};
|
`endif
|
`endif
|
|
|
//TDO is changing on the falling edge of TCK
|
//TDO is changing on the falling edge of tck
|
always @ (negedge TCK or posedge trst)
|
always @ (negedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
begin
|
begin
|
TDOData <= #Tp 0;
|
TDOData <= #Tp 0;
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
| Line 751... |
Line 422... |
else
|
else
|
begin
|
begin
|
if(ShiftDR)
|
if(ShiftDR)
|
begin
|
begin
|
if(IDCODESelected)
|
if(IDCODESelected)
|
TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then TDI is bypassed
|
TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
|
else
|
else
|
if(CHAIN_SELECTSelected)
|
if(CHAIN_SELECTSelected)
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
|
else
|
else
|
if(DEBUGSelected)
|
if(DEBUGSelected)
|
| Line 796... |
Line 467... |
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* CHAIN_SELECT logic *
|
* CHAIN_SELECT logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge TCK or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
|
else
|
else
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
|
| Line 813... |
Line 484... |
* *
|
* *
|
* Register read/write logic *
|
* Register read/write logic *
|
* RISC registers read/write logic *
|
* RISC registers read/write logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
always @ (posedge TCK or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
begin
|
begin
|
ADDR[31:0] <=#Tp 32'h0;
|
ADDR[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
DataOut[31:0] <=#Tp 32'h0;
|
| Line 853... |
Line 524... |
wb_AccessTck <=#Tp 1'b1; //
|
wb_AccessTck <=#Tp 1'b1; //
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one TCK clock period only
|
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
|
RISCAccessTck <=#Tp 1'b0;
|
RISCAccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'b0;
|
wb_AccessTck <=#Tp 1'b0;
|
end
|
end
|
end
|
end
|
|
|
| Line 868... |
Line 539... |
assign wb_sel_o[3:0] = 4'hf;
|
assign wb_sel_o[3:0] = 4'hf;
|
assign wb_cab_o = 1'b0;
|
assign wb_cab_o = 1'b0;
|
|
|
|
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
// Synchronizing the RegAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
.set2(RegAccessTck), .sync_out(RegAccess)
|
);
|
);
|
|
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
// Synchronizing the RISCAccess signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
.set2(RISCAccessTck), .sync_out(RISCAccess)
|
);
|
);
|
|
|
|
|
// Synchronizing the wb_Access signal to wishbone clock
|
// Synchronizing the wb_Access signal to wishbone clock
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
|
);
|
);
|
|
|
|
|
|
|
| Line 1018... |
Line 689... |
**********************************************************************************/
|
**********************************************************************************/
|
`ifdef TRACE_ENABLED
|
`ifdef TRACE_ENABLED
|
|
|
|
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
// Synchronizing the trace read buffer signal to risc_clk_i clock
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(TCK), .reset1(wb_rst_i), .reset2(trst),
|
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
|
);
|
);
|
|
|
|
|
|
|
| Line 1043... |
Line 714... |
* End: Read Trace buffer logic *
|
* End: Read Trace buffer logic *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Bypass logic *
|
|
* *
|
|
**********************************************************************************/
|
|
reg TDOBypassed;
|
|
|
|
always @ (posedge TCK)
|
|
begin
|
|
if(ShiftDR)
|
|
BypassRegister<=#Tp TDI;
|
|
end
|
|
|
|
always @ (negedge TCK)
|
|
begin
|
|
TDOBypassed<=#Tp BypassRegister;
|
|
end
|
|
/**********************************************************************************
|
|
* *
|
|
* End: Bypass logic *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Activating Instructions *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
// Updating JTAG_IR (Instruction Register)
|
|
always @ (posedge TCK or posedge trst)
|
|
begin
|
|
if(trst)
|
|
LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
|
|
else
|
|
if(UpdateIR)
|
|
LatchedJTAG_IR <=#Tp JTAG_IR;
|
|
end
|
|
|
|
|
|
|
|
// Updating JTAG_IR (Instruction Register)
|
|
always @ (LatchedJTAG_IR)
|
|
begin
|
|
EXTESTSelected = 0;
|
|
SAMPLE_PRELOADSelected = 0;
|
|
IDCODESelected = 0;
|
|
CHAIN_SELECTSelected = 0;
|
|
INTESTSelected = 0;
|
|
CLAMPSelected = 0;
|
|
CLAMPZSelected = 0;
|
|
HIGHZSelected = 0;
|
|
DEBUGSelected = 0;
|
|
BYPASSSelected = 0;
|
|
|
|
case(LatchedJTAG_IR)
|
|
`EXTEST: EXTESTSelected = 1; // External test
|
|
`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
|
|
`IDCODE: IDCODESelected = 1; // ID Code
|
|
`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
|
|
`INTEST: INTESTSelected = 1; // Internal test
|
|
`CLAMP: CLAMPSelected = 1; // Clamp
|
|
`CLAMPZ: CLAMPZSelected = 1; // ClampZ
|
|
`HIGHZ: HIGHZSelected = 1; // High Z
|
|
`DEBUG: DEBUGSelected = 1; // Debug
|
|
`BYPASS: BYPASSSelected = 1; // BYPASS
|
|
default: BYPASSSelected = 1; // BYPASS
|
|
endcase
|
|
end
|
|
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* Multiplexing TDO and Tristate control *
|
|
* *
|
|
**********************************************************************************/
|
|
wire TDOShifted;
|
|
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
|
|
/**********************************************************************************
|
|
* *
|
|
* End: Multiplexing TDO and Tristate control *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
|
|
|
|
// This multiplexer can be expanded with number of user registers
|
|
reg TDOMuxed;
|
|
//always @ (JTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
|
|
always @ (LatchedJTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
|
|
begin
|
|
case(JTAG_IR)
|
|
`IDCODE: // Reading ID code
|
|
begin
|
|
TDOMuxed<=#Tp TDOShifted;
|
|
end
|
|
`CHAIN_SELECT: // Selecting the chain
|
|
begin
|
|
TDOMuxed<=#Tp TDOShifted;
|
|
end
|
|
`DEBUG: // Debug
|
|
begin
|
|
TDOMuxed<=#Tp TDOShifted;
|
|
end
|
|
`SAMPLE_PRELOAD: // Sampling/Preloading
|
|
begin
|
|
TDOMuxed<=#Tp BS_CHAIN_I;
|
|
end
|
|
`EXTEST: // External test
|
|
begin
|
|
TDOMuxed<=#Tp BS_CHAIN_I;
|
|
end
|
|
default: // BYPASS instruction
|
|
begin
|
|
TDOMuxed<=#Tp TDOBypassed;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// Tristate control for tdo_pad_o pin
|
|
//assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
|
|
assign tdo_pad_o = TDOMuxed;
|
|
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
|
|
|
|
/**********************************************************************************
|
|
* *
|
|
* End: Activating Instructions *
|
|
* *
|
|
**********************************************************************************/
|
|
|
|
/**********************************************************************************
|
/**********************************************************************************
|
* *
|
* *
|
* Bit counter *
|
* Bit counter *
|
* *
|
* *
|
**********************************************************************************/
|
**********************************************************************************/
|
|
|
|
|
always @ (posedge TCK or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
BitCounter[7:0]<=#Tp 0;
|
BitCounter[7:0]<=#Tp 0;
|
else
|
else
|
if(ShiftDR)
|
if(ShiftDR)
|
| Line 1282... |
Line 822... |
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
|
`endif
|
`endif
|
);
|
);
|
|
|
// Calculating crc for input data
|
// Calculating crc for input data
|
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
dbg_crc8_d1 crc1 (.Data(tdi), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
.CrcOut(CalculatedCrcIn), .Clk(TCK));
|
.CrcOut(CalculatedCrcIn), .Clk(tck));
|
|
|
// Calculating crc for output data
|
// Calculating crc for output data
|
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
|
.CrcOut(CalculatedCrcOut), .Clk(TCK));
|
.CrcOut(CalculatedCrcOut), .Clk(tck));
|
|
|
|
|
// Generating CrcMatch signal
|
// Generating CrcMatch signal
|
always @ (posedge TCK or posedge trst)
|
always @ (posedge tck or posedge trst)
|
begin
|
begin
|
if(trst)
|
if(trst)
|
CrcMatch <=#Tp 1'b0;
|
CrcMatch <=#Tp 1'b0;
|
else
|
else
|
if(Exit1DR)
|
if(Exit1DR)
|
